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Miller" , Udit Tiwari , Md Sadre Alam , Dmitry Baryshkov , Manivannan Sadhasivam , Bjorn Andersson , Peter Ujfalusi , Michal Simek , Frank Li , Andy Gross , Neil Armstrong , dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, linux-arm-kernel@lists.infradead.org, brgl@kernel.org, Bartosz Golaszewski Subject: Re: [PATCH v20 06/14] dmaengine: qcom: bam_dma: add support for BAM locking Message-ID: References: <20260629-qcom-qce-cmd-descr-v20-0-56f67da84c05@oss.qualcomm.com> <20260629-qcom-qce-cmd-descr-v20-6-56f67da84c05@oss.qualcomm.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260629-qcom-qce-cmd-descr-v20-6-56f67da84c05@oss.qualcomm.com> On Mon, Jun 29, 2026 at 12:01:08PM +0200, Bartosz Golaszewski wrote: > Add support for BAM pipe locking. To that end: when starting DMA on an RX > channel - prepend the existing queue of issued descriptors with an > additional "dummy" command descriptor with the LOCK bit set. Once the > transaction is done (no more issued descriptors), issue one more dummy > descriptor with the UNLOCK bit. > > We *must* wait until the transaction is signalled as done because we > must not perform any writes into config registers while the engine is > busy. > > The dummy writes must be issued into a scratchpad register of the client > so provide a mechanism to communicate the right address via descriptor > metadata. > > Reviewed-by: Manivannan Sadhasivam > Signed-off-by: Bartosz Golaszewski I finally found the time to try this for the qcom_nandc driver on MDM9607 (with scratchpad_addr = nandc->base_phys + NAND_VERSION). It seems to work fine and my initial impression is that it does solve the crashes/corruption when both Linux and the modem access the NAND in parallel. (Hard to reproduce, needs a bit more testing.) Thanks! It feels a bit awkward to call dmaengine_desc_attach_metadata() with the same scratchpad_addr for every descriptor (especially because you store it globally), but I also don't really have a better idea how to pass the address for the dummy register. > --- > drivers/dma/qcom/bam_dma.c | 189 +++++++++++++++++++++++++++++++++++++-- > include/linux/dma/qcom_bam_dma.h | 14 +++ > 2 files changed, 196 insertions(+), 7 deletions(-) > > diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c > index f3e713a5259c2c7c24cfdcec094814eb1202971a..f4f258994264a234f60debd3e66e31a6b35d1dc5 100644 > --- a/drivers/dma/qcom/bam_dma.c > +++ b/drivers/dma/qcom/bam_dma.c > [...] > @@ -919,13 +977,23 @@ static u32 process_channel_irqs(struct bam_device *bdev) > * push back to front of desc_issued so that > * it gets restarted by the work queue. > */ > + > + list_del(&async_desc->desc_node); > if (!async_desc->num_desc) { > - vchan_cookie_complete(&async_desc->vd); > + struct bam_desc_hw *hdesc = async_desc->desc; > + u16 flags = le16_to_cpu(hdesc->flags); > + > + if (flags & (DESC_FLAG_LOCK | DESC_FLAG_UNLOCK)) { > + if (flags & DESC_FLAG_UNLOCK) > + bchan->bam_locked = false; > + bam_dma_free_lock_desc(&async_desc->vd); > + } else { > + vchan_cookie_complete(&async_desc->vd); > + } > } else { > list_add(&async_desc->vd.node, > &bchan->vc.desc_issued); > } > - list_del(&async_desc->desc_node); > } > } > > [...] > @@ -1064,9 +1220,23 @@ static void bam_start_dma(struct bam_chan *bchan) > > lockdep_assert_held(&bchan->vc.lock); > > + vd = vchan_next_desc(&bchan->vc); > if (!vd) > return; > > + /* > + * Wrap the issued work with a LOCK/UNLOCK pair exactly once, at the > + * start of a fresh sequence and only when there is real work to lock > + * around. On a re-entry after a full FIFO, we see the BAM is locked > + * and must not add another pair we simply continue loading the > + * remainder of the same locked sequence. > + */ > + if (!bchan->bam_locked) { > + ret = bam_setup_pipe_lock(bchan); > + if (ret == 0 && bchan->bam_locked) > + vd = vchan_next_desc(&bchan->vc); > + } I *suspect* though that Sashiko is right about the new race condition here if new descriptors are queued while the hardware is busy processing a locked sequence. https://sashiko.dev/#/patchset/20260629-qcom-qce-cmd-descr-v20-0-56f67da84c05%40oss.qualcomm.com?part=6 Any idea how to fix this? Thanks, Stephan