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Current controller driver supports up to 8 read and > write channels only. In order to utilize all the channels the > controller driver need to have the channel related structs > and variables as per the number of channels supported by IP. > Following changes are made to enable 64 Read / 64 Write > channel support: > > o Defined HDMA specific macros to reflect the channel count. > o The count of ll_regions and dt_regions in dw_edma_chip and > dw_edma_pcie_data shall be in accordance to number of read > and write channels. > o In dw_edma_probe() configure the channels as per the channels > of the IP used. > o Changed mask types to u64 for higher channel counts. > > Signed-off-by: Devendra K Verma > --- ... > struct dw_edma_irq { > struct msi_msg msi; > - u32 wr_mask; > - u32 rd_mask; > struct dw_edma *dw; > + > + DECLARE_BITMAP(wr_mask, 64); > + DECLARE_BITMAP(rd_mask, 64); Nit: Please macro HDMA_MAX_RD_CH and HDMA_MAX_WD_CH > }; > ... > @@ -252,7 +252,7 @@ dw_edma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, > } > > val = dw_edma_v0_core_status_done_int(dw, dir); > - val &= mask; > + val &= *mask; > for_each_set_bit(pos, &val, total) { > chan = &dw->chan[pos + off]; > > @@ -263,7 +263,7 @@ dw_edma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, > } > > val = dw_edma_v0_core_status_abort_int(dw, dir); > - val &= mask; > + val &= *mask; It should be fine if sparse don't report warning. Frank > for_each_set_bit(pos, &val, total) { > chan = &dw->chan[pos + off]; > > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c > index 632abb8b481c..0181bd276e22 100644 > --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c > +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c > @@ -53,13 +53,24 @@ __dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch) > static void dw_hdma_v0_core_off(struct dw_edma *dw) > { > int id; > + enum dw_edma_dir dir; > +/HDMA_MAX_RD_CH > + dir = EDMA_DIR_WRITE; > + for (id = 0; id < dw->wr_ch_cnt; id++) { > + SET_CH_32(dw, dir, id, int_setup, > + HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); > + SET_CH_32(dw, dir, id, int_clear, > + HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); > + SET_CH_32(dw, dir, id, ch_en, 0); > + } > > - for (id = 0; id < HDMA_V0_MAX_NR_CH; id++) { > - SET_BOTH_CH_32(dw, id, int_setup, > - HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); > - SET_BOTH_CH_32(dw, id, int_clear, > - HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); > - SET_BOTH_CH_32(dw, id, ch_en, 0); > + dir = EDMA_DIR_READ; > + for (id = 0; id < dw->rd_ch_cnt; id++) { > + SET_CH_32(dw, dir, id, int_setup, > + HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); > + SET_CH_32(dw, dir, id, int_clear, > + HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); > + SET_CH_32(dw, dir, id, ch_en, 0); > } > } > > @@ -118,7 +129,7 @@ dw_hdma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, > unsigned long total, pos, val; > irqreturn_t ret = IRQ_NONE; > struct dw_edma_chan *chan; > - unsigned long off, mask; > + unsigned long off, *mask; > > if (dir == EDMA_DIR_WRITE) { > total = dw->wr_ch_cnt; > @@ -130,7 +141,7 @@ dw_hdma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, > mask = dw_irq->rd_mask; > } > > - for_each_set_bit(pos, &mask, total) { > + for_each_set_bit(pos, mask, total) { > chan = &dw->chan[pos + off]; > > val = dw_hdma_v0_core_status_int(chan); > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-regs.h b/drivers/dma/dw-edma/dw-hdma-v0-regs.h > index 7759ba9b4850..48e40efceb2e 100644 > --- a/drivers/dma/dw-edma/dw-hdma-v0-regs.h > +++ b/drivers/dma/dw-edma/dw-hdma-v0-regs.h > @@ -11,7 +11,7 @@ > > #include > > -#define HDMA_V0_MAX_NR_CH 8 > +#define HDMA_V0_MAX_NR_CH 64 > #define HDMA_V0_CH_EN BIT(0) > #define HDMA_V0_LOCAL_ABORT_INT_EN BIT(6) > #define HDMA_V0_REMOTE_ABORT_INT_EN BIT(5) > diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h > index 1fafd5b0e315..da7a5cc93ad4 100644 > --- a/include/linux/dma/edma.h > +++ b/include/linux/dma/edma.h > @@ -14,6 +14,8 @@ > > #define EDMA_MAX_WR_CH 8 > #define EDMA_MAX_RD_CH 8 > +#define HDMA_MAX_WR_CH 64 > +#define HDMA_MAX_RD_CH 64 > > struct dw_edma; > > @@ -89,12 +91,12 @@ struct dw_edma_chip { > u16 ll_wr_cnt; > u16 ll_rd_cnt; > /* link list address */ > - struct dw_edma_region ll_region_wr[EDMA_MAX_WR_CH]; > - struct dw_edma_region ll_region_rd[EDMA_MAX_RD_CH]; > + struct dw_edma_region ll_region_wr[HDMA_MAX_WR_CH]; > + struct dw_edma_region ll_region_rd[HDMA_MAX_RD_CH]; > > /* data region */ > - struct dw_edma_region dt_region_wr[EDMA_MAX_WR_CH]; > - struct dw_edma_region dt_region_rd[EDMA_MAX_RD_CH]; > + struct dw_edma_region dt_region_wr[HDMA_MAX_WR_CH]; > + struct dw_edma_region dt_region_rd[HDMA_MAX_RD_CH]; > > /* interrupt emulation */ > int db_irq; > -- > 2.43.0 >