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The > sq contains three control structures shared with hardware: descriptor > ring, write index, and context status block (which contains the read > index). Define the hardware context-status and generic descriptor > layouts, including assertions for their sizes. > > The descriptor ring requires only 64-byte alignment, so it's practical > to implement it as a flexible array member. The write index and context > status are small enough to place in the struct as well, so we have a > single DMA coherent allocation to manage. > > Signed-off-by: Nathan Lynch > --- Reviewed-by: Frank Li