From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v1] dmaengine: tegra: Use relaxed versions of readl/writel From: Jon Hunter Message-Id: Date: Fri, 26 Apr 2019 12:13:37 +0100 To: Dmitry Osipenko , Laxman Dewangan , Vinod Koul , Thierry Reding Cc: dmaengine@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org List-ID: T24gMjYvMDQvMjAxOSAxMTo0NSwgRG1pdHJ5IE9zaXBlbmtvIHdyb3RlOgo+IDI2LjA0LjIwMTkg MTI6NTIsIEpvbiBIdW50ZXIg0L/QuNGI0LXRgjoKPj4KPj4gT24gMjUvMDQvMjAxOSAwMDoxNywg RG1pdHJ5IE9zaXBlbmtvIHdyb3RlOgo+Pj4gVGhlIHJlYWRsL3dyaXRlbCBmdW5jdGlvbnMgYXJl IGluc2VydGluZyBtZW1vcnkgYmFycmllciBpbiBvcmRlciB0bwo+Pj4gZW5zdXJlIHRoYXQgbWVt b3J5IHN0b3JlcyBhcmUgY29tcGxldGVkLiBPbiBUZWdyYTIwIGFuZCBUZWdyYTMwIHRoaXMKPj4+ IHJlc3VsdHMgaW4gTDIgY2FjaGUgc3luY2luZyB3aGljaCBpc24ndCBhIGNoZWFwZXN0IG9wZXJh dGlvbi4gVGhlCj4+PiB0ZWdyYTIwLWFwYi1kbWEgZHJpdmVyIGRvZXNuJ3QgbmVlZCB0byBzeW5j aHJvbml6ZSBnZW5lcmljIG1lbW9yeQo+Pj4gYWNjZXNzZXMsIGhlbmNlIHVzZSB0aGUgcmVsYXhl ZCB2ZXJzaW9ucyBvZiB0aGUgZnVuY3Rpb25zLgo+Pgo+PiBEbyB5b3UgbWVhbiBkZXZpY2UtaW8g YWNjZXNzZXMgaGVyZSBhcyB0aGlzIGlzIG5vdCBnZW5lcmljIG1lbW9yeT8KPiAKPiBZZXMuIFRo ZSBJT01FTSBhY2Nlc3NlcyB3aXRoaW4gYXJlIGFsd2F5cyBvcmRlcmVkIGFuZCB1bmNhY2hlZCwg d2hpbGUKPiBnZW5lcmljIG1lbW9yeSBhY2Nlc3NlcyBhcmUgb3V0LW9mLW9yZGVyIGFuZCBjYWNo ZWQuCj4gCj4+IEFsdGhvdWdoIHRoZXJlIG1heSBub3QgYmUgYW55IGlzc3VlcyB3aXRoIHRoaXMg Y2hhbmdlLCBJIHRoaW5rIEkgbmVlZCBhCj4+IGJpdCBtb3JlIGNvbnZpbmNpbmcgdGhhdCB3ZSBz aG91bGQgZG8gdGhpcyBnaXZlbiB0aGF0IHdlIGhhdmUgaGFkIGl0Cj4+IHRoaXMgd2F5IGZvciBz b21ldGltZSBhbmQgSSB3b3VsZCBub3QgbGlrZSB0byBzZWUgdXMgaW50cm9kdWNlIGFueQo+PiBy ZWdyZXNzaW9ucyBhcyB0aGlzIHBvaW50IHdpdGhvdXQgYmVpbmcgMTAwJSBjZXJ0YWluIHdlIHdv dWxkIG5vdC4KPj4gSWRlYWxseSwgaWYgSSBoYWQgc29tZSBnb29kIGV4dGVuc2l2ZSB0ZXN0cyBJ IGNvdWxkIHJ1biB0byBoYW1tZXIgdGhlCj4+IERNQSBmb3IgYWxsIGNvbmZpZ3VyYXRpb25zIHdp dGggZGlmZmVyZW50IGNvbWJpbmF0aW9ucyBvZiBjaGFubmVscwo+PiBydW5uaW5nIHNpbXVsdGFu ZW91c2x5IHRoZW4gd2UgY291bGQgdGVzdCB0aGlzLCBidXQgcmlnaHQgbm93IEkgZG9uJ3QgOi0o Cj4+Cj4+IEhhdmUgeW91IC4uLgo+PiAxLiBUZXN0ZWQgYm90aCBjeWNsaWMgYW5kIHNjYXR0ZXIt Z2F0aGVyIHRyYW5zZmVycz8KPj4gMi4gU3RyZXNzIHRlc3RlZCBzaW11bHRhbmVvdXMgdHJhbnNm ZXJzIHdpdGggdmFyaW91cyBkaWZmZXJlbnQKPj4gICAgY29uZmlndXJhdGlvbnM/Cj4+IDMuIFF1 YW50aWZpZWQgdGhlIGFjdHVhbCBwZXJmb3JtYW5jZSBiZW5lZml0IG9mIHRoaXMgY2hhbmdlIHNv IHdlIGNhbgo+PiAgICB1bmRlcnN0YW5kIGhvdyBtdWNoIG9mIGEgcGVyZm9ybWFuY2UgYm9vc3Qg dGhpcyBvZmZlcnM/Cj4gCj4gQWN0dWFsbHkgSSBmb3VuZCBhIGNhc2Ugd2hlcmUgdGhpcyBjaGFu Z2UgY2F1c2VzIGEgcHJvYmxlbSwgSSdtIHNlZWluZwo+IEkyQyB0cmFuc2ZlciB0aW1lb3V0IGZv ciB0b3VjaHNjcmVlbiBhbmQgaXQgYnJlYWtzIHRoZSB0b3VjaCBpbnB1dC4KPiBJbmRlZWQsIEkg aGF2ZW4ndCB0ZXN0ZWQgdGhpcyBwYXRjaCB2ZXJ5IHdlbGwuCj4gCj4gQW5kIHRoZSBmaXggaXMg dGhpczoKPiAKPiBAQCAtMTU5Miw2ICsxNTkyLDggQEAgc3RhdGljIGludCB0ZWdyYV9kbWFfcnVu dGltZV9zdXNwZW5kKHN0cnVjdCBkZXZpY2UKPiAqZGV2KQo+ICAJCQkJCQkgIFRFR1JBX0FQQkRN QV9DSEFOX1dDT1VOVCk7Cj4gIAl9Cj4gCj4gKwlkc2IoKTsKPiArCj4gIAljbGtfZGlzYWJsZV91 bnByZXBhcmUodGRtYS0+ZG1hX2Nsayk7Cj4gCj4gIAlyZXR1cm4gMDsKPiAKPiAKPiBBcHBhcmVu dGx5IHRoZSBwcm9ibGVtIGlzIHRoYXQgQ0xLL0RNQSAoUFBTQi9BUEIpIGFjY2Vzc2VzIGFyZQo+ IGluY29oZXJlbnQgYW5kIENQVSBkaXNhYmxlcyBjbG9jayBiZWZvcmUgd3JpdGVzIGFyZSByZWFj aGluZyBETUEgY29udHJvbGxlci4KPiAKPiBJJ2Qgc2F5IHRoYXQgY3ljbGljIGFuZCBzY2F0dGVy LWdhdGhlciB0cmFuc2ZlcnMgYXJlIG5vdyB0ZXN0ZWQuIEkgYWxzbwo+IG1hZGUgc29tZSBtb3Jl IHRlc3Rpbmcgb2Ygc2ltdWx0YW5lb3VzIHRyYW5zZmVycy4KPiAKPiBRdWFudGlmeWluZyBwZXJm b3JtYW5jZSBwcm9iYWJseSB3b24ndCBiZSBlYXN5IHRvIG1ha2UgYXMgdGhlIERNQQo+IHJlYWQv d3JpdGVzIGFyZSBub3Qgb24gYW55IGtpbmQgb2YgY29kZSdzIGhvdC1wYXRoLgoKU28gd2h5IG1h a2UgdGhlIGNoYW5nZT8KPiBKb24sIGFyZSB5b3Ugc3RpbGwgaW5zaXN0aW5nIGFib3V0IHRvIGRy b3AgdGhpcyBwYXRjaCBvciB5b3Ugd2lsbCBiZQo+IGZpbmUgd2l0aCB0aGUgdjIgdGhhdCB3aWxs IGhhdmUgdGhlIGRzYigpIGluIHBsYWNlPwoKSWYgd2UgY2FuJ3QgcXVhbnRpZnkgdGhlIHBlcmZv cm1hbmNlIGdhaW4sIHRoZW4gaXQgaXMgZGlmZmljdWx0IHRvCmp1c3RpZnkgdGhlIGNoYW5nZS4g SSB3b3VsZCBhbHNvIGJlIGNvbmNlcm5lZCBpZiB0aGF0IGlzIHRoZSBvbmx5IHBsYWNlCndlIG5l ZWQgYW4gZXhwbGljaXQgZHNiLgoKQ2hlZXJzCkpvbgo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, T_DKIMWL_WL_HIGH autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13472C43218 for ; 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by hqpgpgate102.nvidia.com on Fri, 26 Apr 2019 04:13:40 -0700 Received: from [10.21.132.148] (172.20.13.39) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 26 Apr 2019 11:13:38 +0000 Subject: Re: [PATCH v1] dmaengine: tegra: Use relaxed versions of readl/writel To: Dmitry Osipenko , Laxman Dewangan , Vinod Koul , Thierry Reding CC: , , References: <20190424231708.21219-1-digetx@gmail.com> <4a315b63-bc71-3c3e-f1ae-8638bcf4033d@gmail.com> From: Jon Hunter Message-ID: Date: Fri, 26 Apr 2019 12:13:37 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <4a315b63-bc71-3c3e-f1ae-8638bcf4033d@gmail.com> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL103.nvidia.com (172.20.187.11) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="UTF-8" Content-Language: en-US Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1556277227; bh=O/GAZj9r0fT77AziCi8BIUhr0zpYSUaCjsqVbQvWxNo=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=A0CPH/SJVtOlSPOSszQYDZd0C6X66NRGXuSvxP1l6gaQHKYJsaWAQQTIGERJntQ6b zJz4XL/eXrb7+xdLsMLJwLTn2aKAzUAkouWMo2HyQdp+EWdkNX1BXp6hbnhIJOMrci 99uFOEL9QIS5Q9FTXJ4AY/4xUfFGjscNEJmIvUKipqDQgwWVf6xxhrFa+LfGC8pQx9 uPXrcvA8OPW4auaVU7TO24A9TGE/8sPKJhMtWYFojYv3ahB/BmwMxS3rhwNE3YO/H2 DY9AqT19P2a0sx2de0gnzyPOPrc9ZITUyWabrukDRR9ke5qZP8E0Y09IoKIqX/I78o D2sT4UENqIXPg== Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Message-ID: <20190426111337.gJqmoKw138Rv81xztKOm3CnZikM9U-4FMd6l57X9ysY@z> On 26/04/2019 11:45, Dmitry Osipenko wrote: > 26.04.2019 12:52, Jon Hunter =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >> >> On 25/04/2019 00:17, Dmitry Osipenko wrote: >>> The readl/writel functions are inserting memory barrier in order to >>> ensure that memory stores are completed. On Tegra20 and Tegra30 this >>> results in L2 cache syncing which isn't a cheapest operation. The >>> tegra20-apb-dma driver doesn't need to synchronize generic memory >>> accesses, hence use the relaxed versions of the functions. >> >> Do you mean device-io accesses here as this is not generic memory? >=20 > Yes. The IOMEM accesses within are always ordered and uncached, while > generic memory accesses are out-of-order and cached. >=20 >> Although there may not be any issues with this change, I think I need a >> bit more convincing that we should do this given that we have had it >> this way for sometime and I would not like to see us introduce any >> regressions as this point without being 100% certain we would not. >> Ideally, if I had some good extensive tests I could run to hammer the >> DMA for all configurations with different combinations of channels >> running simultaneously then we could test this, but right now I don't :-= ( >> >> Have you ... >> 1. Tested both cyclic and scatter-gather transfers? >> 2. Stress tested simultaneous transfers with various different >> configurations? >> 3. Quantified the actual performance benefit of this change so we can >> understand how much of a performance boost this offers? >=20 > Actually I found a case where this change causes a problem, I'm seeing > I2C transfer timeout for touchscreen and it breaks the touch input. > Indeed, I haven't tested this patch very well. >=20 > And the fix is this: >=20 > @@ -1592,6 +1592,8 @@ static int tegra_dma_runtime_suspend(struct device > *dev) > TEGRA_APBDMA_CHAN_WCOUNT); > } >=20 > + dsb(); > + > clk_disable_unprepare(tdma->dma_clk); >=20 > return 0; >=20 >=20 > Apparently the problem is that CLK/DMA (PPSB/APB) accesses are > incoherent and CPU disables clock before writes are reaching DMA controll= er. >=20 > I'd say that cyclic and scatter-gather transfers are now tested. I also > made some more testing of simultaneous transfers. >=20 > Quantifying performance probably won't be easy to make as the DMA > read/writes are not on any kind of code's hot-path. So why make the change? > Jon, are you still insisting about to drop this patch or you will be > fine with the v2 that will have the dsb() in place? If we can't quantify the performance gain, then it is difficult to justify the change. I would also be concerned if that is the only place we need an explicit dsb. Cheers Jon --=20 nvpublic