[PATCH v2 0/4] agilex5: Update agilex5 device tree and device tree bindings

[PATCH v2 0/4] agilex5: Update agilex5 device tree and device tree bindings

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

This patch set is to update Agilex5 device tree and the related device
tree bindings.
Altera Agilex5 address bus only supports up to 40 bits. This patch set
adds support for a new property that is used to configure the
dma-bit-mask if its present in the device tree

This patch set includes the following changes:
-Add property for dw-axi-dmac that configures the dma-bit-mask to the
required bits.
-Update cdns nand dt binding with iommus and dma-coherent as an optional
property.
-Update Agilex5 dtsi and dts.
-Add implementation to set dma bit-mask to value configured in dma
bit-mask quirk if present.

v2:
-Fixed build errors and warnings in dw-axi-dmac.

Adrian Ng Ho Yin (4):
  dt-bindings: dma: snps,dw-axi-dmac: Add iommus dma-coherent and dma
    bit-mask quirk
  dt-bindings: mtd: cadence: Add iommus and dma-coherent properties
  arm64: dts: socfpga: agilex5: Update Agilex5 DTSI and DTS
  dma: dw-axi-dmac: Add support for dma-bit-mask property

 .../bindings/dma/snps,dw-axi-dmac.yaml        | 13 +++++++++++
 .../devicetree/bindings/mtd/cdns,hp-nfc.yaml  |  5 +++++
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 22 +++++++++++++++++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  4 ++++
 .../dma/dw-axi-dmac/dw-axi-dmac-platform.c    | 14 ++++++++++--
 5 files changed, 56 insertions(+), 2 deletions(-)

-- 
2.49.GIT

[PATCH v2 1/4] dt-bindings: dma: snps,dw-axi-dmac: Add iommus dma-coherent and dma bit-mask quirk

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Intel Agilex5 address bus only supports up to 40 bits. Add dma-bit-mask
property to allow configuration of dma bit-mask size. Add iommu property
for SMMU support. Add dma-coherent property for cache coherent support.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altrera.com>
---
 .../devicetree/bindings/dma/snps,dw-axi-dmac.yaml   | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index 935735a59afd..f0a54a1031e7 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -42,6 +42,9 @@ properties:
     minItems: 1
     maxItems: 8
 
+  iommus:
+    maxItems: 1
+
   clocks:
     items:
       - description: Bus Clock
@@ -61,6 +64,8 @@ properties:
 
   dma-noncoherent: true
 
+  dma-coherent: true
+
   resets:
     minItems: 1
     maxItems: 2
@@ -101,6 +106,14 @@ properties:
     minimum: 1
     maximum: 256
 
+  snps,dma-bit-mask:
+    description:
+      Defines the number of addressable bits for DMA.
+      If this property is missing, the default 64bit will be used.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 32
+    maximum: 64
+
 required:
   - compatible
   - reg
-- 
2.49.GIT

Re: [PATCH v2 1/4] dt-bindings: dma: snps,dw-axi-dmac: Add iommus dma-coherent and dma bit-mask quirk

[Conor Dooley]

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On Mon, May 19, 2025 at 01:09:38PM +0800, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Intel Agilex5 address bus only supports up to 40 bits. Add dma-bit-mask
> property to allow configuration of dma bit-mask size. Add iommu property
> for SMMU support. Add dma-coherent property for cache coherent support.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> Reviewed-by: Matthew Gerlach <matthew.gerlach@altrera.com>
> ---
>  .../devicetree/bindings/dma/snps,dw-axi-dmac.yaml   | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> index 935735a59afd..f0a54a1031e7 100644
> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> @@ -42,6 +42,9 @@ properties:
>      minItems: 1
>      maxItems: 8
>  
> +  iommus:
> +    maxItems: 1
> +
>    clocks:
>      items:
>        - description: Bus Clock
> @@ -61,6 +64,8 @@ properties:
>  
>    dma-noncoherent: true
>  
> +  dma-coherent: true
> +
>    resets:
>      minItems: 1
>      maxItems: 2
> @@ -101,6 +106,14 @@ properties:
>      minimum: 1
>      maximum: 256
>  
> +  snps,dma-bit-mask:

This property seems incorrectly named to me, from the description this
does not seem like a bitmask cos you cannot have a 64-bit bitmask in a
u32... Instead, this property is being fed into the DMA_BIT_MASK()
macro, and is actually just the number of bits to use for dma (as the
description correctly points out). Please adjust the naming accordingly.

> +    description:
> +      Defines the number of addressable bits for DMA.
> +      If this property is missing, the default 64bit will be used.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 32
> +    maximum: 64

Missing a default: 64, that's what you should do rather than mention in
text form.

> +
>  required:
>    - compatible
>    - reg
> -- 
> 2.49.GIT
> 

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[PATCH v2 2/4] dt-bindings: mtd: cadence: Add iommus and dma-coherent properties

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Update bindings to include iommus and dma-coherent as an optional
properties.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altrera.com>
---
 Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
index e1f4d7c35a88..367257a227b1 100644
--- a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
+++ b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
@@ -40,6 +40,11 @@ properties:
   dmas:
     maxItems: 1
 
+  dma-coherent: true
+
+  iommus:
+    maxItems: 1
+
   cdns,board-delay-ps:
     description: |
       Estimated Board delay. The value includes the total round trip
-- 
2.49.GIT

[PATCH v2 3/4] arm64: dts: socfpga: agilex5: Update Agilex5 DTSI and DTS

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Add SMMU node in Agilex5 DTSI and enable it in socdk DTS.
Add IOMMU support to the Agilex5 DMA controllers by adding the iommus,
dma-coherent, and dma-bit-mask properties to the device tree nodes.
Add IOMMU support Agilex5 NAND controller by adding iommus and
dma-coherent properties.
Add IOMMU support Agilex5 DWC2 controller by adding iommus property.
Add ADP support for Agilex5 DWC2 controller by adding otg-rev property.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altrera.com>
---
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 22 +++++++++++++++++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  4 ++++
 2 files changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 51c6e19e40b8..61a0a24cda22 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -272,6 +272,8 @@ nand: nand-controller@10b80000 {
 			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clkmgr AGILEX5_NAND_NF_CLK>;
 			cdns,board-delay-ps = <4830>;
+			iommus = <&smmu 4>;
+			dma-coherent;
 			status = "disabled";
 		};
 
@@ -291,6 +293,7 @@ dmac0: dma-controller@10db0000 {
 			clock-names = "core-clk", "cfgr-clk";
 			interrupt-parent = <&intc>;
 			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			iommus = <&smmu 8>;
 			#dma-cells = <1>;
 			dma-channels = <4>;
 			snps,dma-masters = <1>;
@@ -298,6 +301,8 @@ dmac0: dma-controller@10db0000 {
 			snps,block-size = <32767 32767 32767 32767>;
 			snps,priority = <0 1 2 3>;
 			snps,axi-max-burst-len = <8>;
+			snps,dma-bit-mask = <40>;
+			dma-coherent;
 		};
 
 		dmac1: dma-controller@10dc0000 {
@@ -308,6 +313,7 @@ dmac1: dma-controller@10dc0000 {
 			clock-names = "core-clk", "cfgr-clk";
 			interrupt-parent = <&intc>;
 			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+			iommus = <&smmu 9>;
 			#dma-cells = <1>;
 			dma-channels = <4>;
 			snps,dma-masters = <1>;
@@ -315,6 +321,8 @@ dmac1: dma-controller@10dc0000 {
 			snps,block-size = <32767 32767 32767 32767>;
 			snps,priority = <0 1 2 3>;
 			snps,axi-max-burst-len = <8>;
+			snps,dma-bit-mask = <40>;
+			dma-coherent;
 		};
 
 		rst: rstmgr@10d11000 {
@@ -323,6 +331,18 @@ rst: rstmgr@10d11000 {
 			#reset-cells = <1>;
 		};
 
+		smmu: iommu@16000000 {
+			compatible = "arm,smmu-v3";
+			reg = <0x16000000 0x30000>;
+			interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "eventq", "gerror", "priq";
+			dma-coherent;
+			#iommu-cells = <1>;
+			status = "disabled";
+		};
+
 		spi0: spi@10da4000 {
 			compatible = "snps,dw-apb-ssi";
 			reg = <0x10da4000 0x1000>;
@@ -423,8 +443,10 @@ usb0: usb@10b00000 {
 			phy-names = "usb2-phy";
 			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
 			reset-names = "dwc2", "dwc2-ecc";
+			iommus = <&smmu 6>;
 			clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>;
 			clock-names = "otg";
+			otg-rev = <0x0200>;
 			status = "disabled";
 		};
 
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index c533e5a3a610..d64eb14ccee0 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -25,6 +25,10 @@ &osc1 {
 	clock-frequency = <25000000>;
 };
 
+&smmu {
+	status = "okay";
+};
+
 &uart0 {
 	status = "okay";
 };
-- 
2.49.GIT

[PATCH v2 4/4] dma: dw-axi-dmac: Add support for dma-bit-mask property

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Intel Agilex5 address bus only supports up to 40 bits. Add dma-bit-mask
property support where configure dma-bit-mask based on dma-bit-mask
property or fallback to default value if property is not present.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altrera.com>

v2:
-Fix build errors and warning
---
 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index b23536645ff7..aa6e66dd67f7 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -265,13 +265,23 @@ static inline bool axi_chan_is_hw_enable(struct axi_dma_chan *chan)
 static void axi_dma_hw_init(struct axi_dma_chip *chip)
 {
 	int ret;
-	u32 i;
+	u32 i, tmp;
 
 	for (i = 0; i < chip->dw->hdata->nr_channels; i++) {
 		axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
 		axi_chan_disable(&chip->dw->chan[i]);
 	}
-	ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
+
+	ret = device_property_read_u32(chip->dev, "snps,dma-bit-mask", &tmp);
+	if (ret)
+		ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
+	else {
+		if (tmp == 0 || tmp < 32 || tmp > 64)
+			dev_err(chip->dev, "Invalid dma bit mask\n");
+
+		ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(tmp));
+	}
+
 	if (ret)
 		dev_warn(chip->dev, "Unable to set coherent mask\n");
 }
-- 
2.49.GIT