[PATCH v3 0/3] Add iommu supports

[Khairul Anuar Romli <khairul.anuar.romli@altera.com>]

This patch series adds IOMMU support for the Agilex5 platform by:

- Updating the device tree bindings for:
  - Cadence HP NAND controller (`cdns,hp-nfc`)
  - Synopsys DesignWare AXI DMA controller (`snps,dw-axi-dmac`)
  to accept the `iommus` property.

- Adding the SMMU (System Memory Management Unit) node to the Agilex5
  device tree and wiring up the IOMMU properties to the supported
  peripherals:
  - NAND controller
  - DMA controller
  - SPI controller

The Agilex5 SoC includes an ARM SMMU v3 with dedicated Translation Buffer
Units (TBUs) for peripherals. These allow for hardware-enforced DMA
address translation and memory isolation using the IOMMU framework.

Enabling IOMMU support ensures proper integration of these devices in
virtualized or secure environments, and aligns the platform with ARM’s
architectural requirements.

---
Changes in v3:
	- Refined commit messages with detailed hardware descriptions.
	- Clarified which peripherals are covered in the DT changes.
Changes in v2:
	- Add more description in the commit message body to clarify
	  device required for this changes.
---
Khairul Anuar Romli (3):
  dt-bindings: mtd: cdns,hp-nfc: Add iommu property
  dt-bindings: dma: snps,dw-axi-dmac: Add iommu property
  arm64: dts: socfpga: agilex5: Add SMMU nodes

 .../bindings/dma/snps,dw-axi-dmac.yaml           |  3 +++
 .../devicetree/bindings/mtd/cdns,hp-nfc.yaml     |  3 +++
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi   | 16 ++++++++++++++++
 3 files changed, 22 insertions(+)

-- 
2.35.3