* [PATCH v2 1/8] dt-bindings: dma: marvell,mmp-dma: Add SpacemiT K1 PDMA support
2025-07-01 5:36 [PATCH v2 0/8] dmaengine: mmp_pdma: Add SpacemiT K1 SoC support with 64-bit addressing Guodong Xu
@ 2025-07-01 5:36 ` Guodong Xu
2025-07-01 7:35 ` Krzysztof Kozlowski
2025-07-01 5:36 ` [PATCH v2 2/8] dmaengine: mmp_pdma: Add optional clock support Guodong Xu
` (6 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Guodong Xu @ 2025-07-01 5:36 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Duje Mihanović, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: Alex Elder, Vivian Wang, dmaengine, devicetree, linux-kernel,
linux-riscv, spacemit, Guodong Xu
Add "spacemit,k1-pdma" compatible string to support SpacemiT K1 PDMA
controller. This variant requires:
- clocks: Clock controller for the DMA
- resets: Reset controller for the DMA
Also add explicit #dma-cells property definition with proper constraints:
- 2 cells for marvell,pdma-1.0 and spacemit,k1-pdma
- (request number + unused)
- 1 cell for other variants
- (request number only)
This fixes "make dtbs_check W=3" warnings about unevaluated properties.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2:
- Used more specific compatible string "spacemit,k1-pdma"
- Enhanced DT bindings with conditional constraints:
- clocks/resets properties only required for SpacemiT K1
- #dma-cells set to 2 for marvell,pdma-1.0 and spacemit,k1-pdma
- #dma-cells set to 1 for other variants, ie.
marvell,adma-1.0 and marvell,pxa910-squ
---
.../devicetree/bindings/dma/marvell,mmp-dma.yaml | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/marvell,mmp-dma.yaml b/Documentation/devicetree/bindings/dma/marvell,mmp-dma.yaml
index d447d5207be0436bc7fb648dffe31f8b780b491d..7b5f7ccfc9dbb69bfef250146cba5434548f3702 100644
--- a/Documentation/devicetree/bindings/dma/marvell,mmp-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/marvell,mmp-dma.yaml
@@ -18,6 +18,7 @@ properties:
- marvell,pdma-1.0
- marvell,adma-1.0
- marvell,pxa910-squ
+ - spacemit,k1-pdma
reg:
maxItems: 1
@@ -32,6 +33,19 @@ properties:
A phandle to the SRAM pool
$ref: /schemas/types.yaml#/definitions/phandle
+ clocks:
+ description: Clock for the controller
+ maxItems: 1
+
+ resets:
+ description: Reset controller for the DMA controller
+ maxItems: 1
+
+ '#dma-cells':
+ description:
+ DMA specifier, consisting of a phandle to DMA controller plus the
+ following integer cells
+
'#dma-channels':
deprecated: true
@@ -52,12 +66,47 @@ allOf:
contains:
enum:
- marvell,pdma-1.0
+ - spacemit,k1-pdma
then:
properties:
asram: false
else:
required:
- asram
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: spacemit,k1-pdma
+ then:
+ required:
+ - clocks
+ - resets
+ else:
+ properties:
+ clocks: false
+ resets: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - marvell,pdma-1.0
+ - spacemit,k1-pdma
+ then:
+ properties:
+ '#dma-cells':
+ const: 2
+ description:
+ The first cell contains the DMA request number for the peripheral
+ device. The second cell is currently unused but must be present for
+ backward compatibility.
+ else:
+ properties:
+ '#dma-cells':
+ const: 1
+ description:
+ The cell contains the DMA request number for the peripheral device.
unevaluatedProperties: false
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v2 1/8] dt-bindings: dma: marvell,mmp-dma: Add SpacemiT K1 PDMA support
2025-07-01 5:36 ` [PATCH v2 1/8] dt-bindings: dma: marvell,mmp-dma: Add SpacemiT K1 PDMA support Guodong Xu
@ 2025-07-01 7:35 ` Krzysztof Kozlowski
2025-07-01 9:52 ` Guodong Xu
0 siblings, 1 reply; 18+ messages in thread
From: Krzysztof Kozlowski @ 2025-07-01 7:35 UTC (permalink / raw)
To: Guodong Xu, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Duje Mihanović, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: Alex Elder, Vivian Wang, dmaengine, devicetree, linux-kernel,
linux-riscv, spacemit
On 01/07/2025 07:36, Guodong Xu wrote:
> Add "spacemit,k1-pdma" compatible string to support SpacemiT K1 PDMA
> controller. This variant requires:
Why is this marvell? This should be explained here, it's really unexpected.
> - clocks: Clock controller for the DMA
> - resets: Reset controller for the DMA
>
> Also add explicit #dma-cells property definition with proper constraints:
> - 2 cells for marvell,pdma-1.0 and spacemit,k1-pdma
> - (request number + unused)
> - 1 cell for other variants
> - (request number only)
>
> This fixes "make dtbs_check W=3" warnings about unevaluated properties.
How can I reproduce these warnings? Looks like this is not relevant
here. Each patch is applied one after another and commit msg must be
correct at this point.
>
> Signed-off-by: Guodong Xu <guodong@riscstar.com>
> ---
> v2:
> - Used more specific compatible string "spacemit,k1-pdma"
> - Enhanced DT bindings with conditional constraints:
> - clocks/resets properties only required for SpacemiT K1
> - #dma-cells set to 2 for marvell,pdma-1.0 and spacemit,k1-pdma
> - #dma-cells set to 1 for other variants, ie.
> marvell,adma-1.0 and marvell,pxa910-squ
> ---
> .../devicetree/bindings/dma/marvell,mmp-dma.yaml | 49 ++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/marvell,mmp-dma.yaml b/Documentation/devicetree/bindings/dma/marvell,mmp-dma.yaml
> index d447d5207be0436bc7fb648dffe31f8b780b491d..7b5f7ccfc9dbb69bfef250146cba5434548f3702 100644
> --- a/Documentation/devicetree/bindings/dma/marvell,mmp-dma.yaml
> +++ b/Documentation/devicetree/bindings/dma/marvell,mmp-dma.yaml
> @@ -18,6 +18,7 @@ properties:
> - marvell,pdma-1.0
> - marvell,adma-1.0
> - marvell,pxa910-squ
> + - spacemit,k1-pdma
>
> reg:
> maxItems: 1
> @@ -32,6 +33,19 @@ properties:
> A phandle to the SRAM pool
> $ref: /schemas/types.yaml#/definitions/phandle
>
> + clocks:
> + description: Clock for the controller
> + maxItems: 1
> +
> + resets:
> + description: Reset controller for the DMA controller
> + maxItems: 1
> +
> + '#dma-cells':
> + description:
> + DMA specifier, consisting of a phandle to DMA controller plus the
> + following integer cells
Why do you need it here? Isn't this coming from dma common schemas?
> +
> '#dma-channels':
> deprecated: true
>
> @@ -52,12 +66,47 @@ allOf:
> contains:
> enum:
> - marvell,pdma-1.0
> + - spacemit,k1-pdma
> then:
> properties:
> asram: false
> else:
> required:
> - asram
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: spacemit,k1-pdma
> + then:
> + required:
> + - clocks
> + - resets
> + else:
> + properties:
> + clocks: false
> + resets: false
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - marvell,pdma-1.0
> + - spacemit,k1-pdma
> + then:
> + properties:
> + '#dma-cells':
> + const: 2
> + description:
> + The first cell contains the DMA request number for the peripheral
> + device. The second cell is currently unused but must be present for
> + backward compatibility.
> + else:
> + properties:
> + '#dma-cells':
> + const: 1
> + description:
> + The cell contains the DMA request number for the peripheral device.
It's getting complicated. I suggest to make your own schema. Then you
would also switch to preferred 'sram' property instead of that legacy
'asram'.
Really, ancient schemas should not be grown for new, completely
different platforms.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 1/8] dt-bindings: dma: marvell,mmp-dma: Add SpacemiT K1 PDMA support
2025-07-01 7:35 ` Krzysztof Kozlowski
@ 2025-07-01 9:52 ` Guodong Xu
2025-07-02 20:38 ` Krzysztof Kozlowski
0 siblings, 1 reply; 18+ messages in thread
From: Guodong Xu @ 2025-07-01 9:52 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Duje Mihanović, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Alex Elder,
Vivian Wang, dmaengine, devicetree, linux-kernel, linux-riscv,
spacemit
Hi, Krzysztof
On Tue, Jul 1, 2025 at 3:35 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 01/07/2025 07:36, Guodong Xu wrote:
> > Add "spacemit,k1-pdma" compatible string to support SpacemiT K1 PDMA
> > controller. This variant requires:
>
> Why is this marvell? This should be explained here, it's really unexpected.
>
SpacemiT K1 SoC uses the same DMA controller as Marvell MMP. They share most
of the registers (and address offsets) and only enhanced in addressing space
capability (from 32bit to 64bit).
Also, spacemit,k1-pdma and marvell,pdma-1.0 use the same driver (mmp_pdma.c),
that's the reason why I chose keeping them in the same binding file.
> > - clocks: Clock controller for the DMA
> > - resets: Reset controller for the DMA
> >
> > Also add explicit #dma-cells property definition with proper constraints:
> > - 2 cells for marvell,pdma-1.0 and spacemit,k1-pdma
> > - (request number + unused)
> > - 1 cell for other variants
> > - (request number only)
> >
> > This fixes "make dtbs_check W=3" warnings about unevaluated properties.
>
> How can I reproduce these warnings? Looks like this is not relevant
> here. Each patch is applied one after another and commit msg must be
> correct at this point.
>
You're absolutely right about the commit message needing to be accurate
at this point. The dtbs_check warnings only occur when compiling board DTS
files that contain nodes with marvell,pdma-1.0 or spacemit,k1-pdma
compatible strings - specifically when PATCH 7 of this series.
I'll revise the commit message to better reflect that this patch enhances
things, rather than claiming it "fixes" warnings at this stage.
>
> >
> > Signed-off-by: Guodong Xu <guodong@riscstar.com>
> > ---
> > v2:
> > - Used more specific compatible string "spacemit,k1-pdma"
> > - Enhanced DT bindings with conditional constraints:
> > - clocks/resets properties only required for SpacemiT K1
> > - #dma-cells set to 2 for marvell,pdma-1.0 and spacemit,k1-pdma
> > - #dma-cells set to 1 for other variants, ie.
> > marvell,adma-1.0 and marvell,pxa910-squ
> > ---
> > .../devicetree/bindings/dma/marvell,mmp-dma.yaml | 49 ++++++++++++++++++++++
> > 1 file changed, 49 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/dma/marvell,mmp-dma.yaml b/Documentation/devicetree/bindings/dma/marvell,mmp-dma.yaml
> > index d447d5207be0436bc7fb648dffe31f8b780b491d..7b5f7ccfc9dbb69bfef250146cba5434548f3702 100644
> > --- a/Documentation/devicetree/bindings/dma/marvell,mmp-dma.yaml
> > +++ b/Documentation/devicetree/bindings/dma/marvell,mmp-dma.yaml
> > @@ -18,6 +18,7 @@ properties:
> > - marvell,pdma-1.0
> > - marvell,adma-1.0
> > - marvell,pxa910-squ
> > + - spacemit,k1-pdma
> >
> > reg:
> > maxItems: 1
> > @@ -32,6 +33,19 @@ properties:
> > A phandle to the SRAM pool
> > $ref: /schemas/types.yaml#/definitions/phandle
> >
> > + clocks:
> > + description: Clock for the controller
> > + maxItems: 1
> > +
> > + resets:
> > + description: Reset controller for the DMA controller
> > + maxItems: 1
> > +
> > + '#dma-cells':
> > + description:
> > + DMA specifier, consisting of a phandle to DMA controller plus the
> > + following integer cells
>
> Why do you need it here? Isn't this coming from dma common schemas?
Thanks for pointing out this. It should be removed.
I will fix it.
> > +
> > '#dma-channels':
> > deprecated: true
> >
> > @@ -52,12 +66,47 @@ allOf:
> > contains:
> > enum:
> > - marvell,pdma-1.0
> > + - spacemit,k1-pdma
> > then:
> > properties:
> > asram: false
> > else:
> > required:
> > - asram
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: spacemit,k1-pdma
> > + then:
> > + required:
> > + - clocks
> > + - resets
> > + else:
> > + properties:
> > + clocks: false
> > + resets: false
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - marvell,pdma-1.0
> > + - spacemit,k1-pdma
> > + then:
> > + properties:
> > + '#dma-cells':
> > + const: 2
> > + description:
> > + The first cell contains the DMA request number for the peripheral
> > + device. The second cell is currently unused but must be present for
> > + backward compatibility.
> > + else:
> > + properties:
> > + '#dma-cells':
> > + const: 1
> > + description:
> > + The cell contains the DMA request number for the peripheral device.
>
>
> It's getting complicated. I suggest to make your own schema. Then you
> would also switch to preferred 'sram' property instead of that legacy
> 'asram'.
>
> Really, ancient schemas should not be grown for new, completely
The reason that they share the same device driver may not be strong enough
compared to what you said here.
> different platforms.
>
Complexity wise, I agree with you. I should admit that I haven't dug into
the history enough. Anyway, unless other people have strong opinion, I will
create a new schema namely spacemit,k1-pdma.yaml
Thanks Krzysztof.
BR,
Guodong
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 1/8] dt-bindings: dma: marvell,mmp-dma: Add SpacemiT K1 PDMA support
2025-07-01 9:52 ` Guodong Xu
@ 2025-07-02 20:38 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2025-07-02 20:38 UTC (permalink / raw)
To: Guodong Xu
Cc: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Duje Mihanović, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Alex Elder,
Vivian Wang, dmaengine, devicetree, linux-kernel, linux-riscv,
spacemit
On 01/07/2025 11:52, Guodong Xu wrote:
> Hi, Krzysztof
>
> On Tue, Jul 1, 2025 at 3:35 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>> On 01/07/2025 07:36, Guodong Xu wrote:
>>> Add "spacemit,k1-pdma" compatible string to support SpacemiT K1 PDMA
>>> controller. This variant requires:
>>
>> Why is this marvell? This should be explained here, it's really unexpected.
>>
>
> SpacemiT K1 SoC uses the same DMA controller as Marvell MMP. They share most
> of the registers (and address offsets) and only enhanced in addressing space
> capability (from 32bit to 64bit).
I hope you got the last comment...
>
> Also, spacemit,k1-pdma and marvell,pdma-1.0 use the same driver (mmp_pdma.c),
> that's the reason why I chose keeping them in the same binding file.
That's moderate reason. I explained here further - don't grow old
bindings with completely new devices, because you keep growing old,
poorer patterns. You have a new device, you can make it right.
...
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + const: spacemit,k1-pdma
>>> + then:
>>> + required:
>>> + - clocks
>>> + - resets
>>> + else:
>>> + properties:
>>> + clocks: false
>>> + resets: false
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + enum:
>>> + - marvell,pdma-1.0
>>> + - spacemit,k1-pdma
>>> + then:
>>> + properties:
>>> + '#dma-cells':
>>> + const: 2
>>> + description:
>>> + The first cell contains the DMA request number for the peripheral
>>> + device. The second cell is currently unused but must be present for
>>> + backward compatibility.
>>> + else:
>>> + properties:
>>> + '#dma-cells':
>>> + const: 1
>>> + description:
>>> + The cell contains the DMA request number for the peripheral device.
>>
>>
>> It's getting complicated. I suggest to make your own schema. Then you
>> would also switch to preferred 'sram' property instead of that legacy
>> 'asram'.
>>
>> Really, ancient schemas should not be grown for new, completely
>
> The reason that they share the same device driver may not be strong enough
> compared to what you said here.
If DMA maintainer(s) reject complexity in driver, then it is fine. But
till that happens, you should rather come with a clean new binding and
don't grow legacy.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 2/8] dmaengine: mmp_pdma: Add optional clock support
2025-07-01 5:36 [PATCH v2 0/8] dmaengine: mmp_pdma: Add SpacemiT K1 SoC support with 64-bit addressing Guodong Xu
2025-07-01 5:36 ` [PATCH v2 1/8] dt-bindings: dma: marvell,mmp-dma: Add SpacemiT K1 PDMA support Guodong Xu
@ 2025-07-01 5:36 ` Guodong Xu
2025-07-01 5:36 ` [PATCH v2 3/8] dmaengine: mmp_pdma: Add optional reset controller support Guodong Xu
` (5 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: Guodong Xu @ 2025-07-01 5:36 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Duje Mihanović, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: Alex Elder, Vivian Wang, dmaengine, devicetree, linux-kernel,
linux-riscv, spacemit, Guodong Xu
Add support for retrieving and enabling an optional clock during
mmp_pdma_probe().
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2: No change.
---
drivers/dma/mmp_pdma.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c
index a95d31103d3063a1d11177a1a37b89ac2fd213e9..4a6dbf55823722d26cc69379d22aaa88fbe19313 100644
--- a/drivers/dma/mmp_pdma.c
+++ b/drivers/dma/mmp_pdma.c
@@ -15,6 +15,7 @@
#include <linux/device.h>
#include <linux/platform_data/mmp_dma.h>
#include <linux/dmapool.h>
+#include <linux/clk.h>
#include <linux/of_dma.h>
#include <linux/of.h>
@@ -1019,6 +1020,7 @@ static int mmp_pdma_probe(struct platform_device *op)
{
struct mmp_pdma_device *pdev;
struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);
+ struct clk *clk;
int i, ret, irq = 0;
int dma_channels = 0, irq_num = 0;
const enum dma_slave_buswidth widths =
@@ -1037,6 +1039,10 @@ static int mmp_pdma_probe(struct platform_device *op)
if (IS_ERR(pdev->base))
return PTR_ERR(pdev->base);
+ clk = devm_clk_get_optional_enabled(pdev->dev, NULL);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
if (pdev->dev->of_node) {
/* Parse new and deprecated dma-channels properties */
if (of_property_read_u32(pdev->dev->of_node, "dma-channels",
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 3/8] dmaengine: mmp_pdma: Add optional reset controller support
2025-07-01 5:36 [PATCH v2 0/8] dmaengine: mmp_pdma: Add SpacemiT K1 SoC support with 64-bit addressing Guodong Xu
2025-07-01 5:36 ` [PATCH v2 1/8] dt-bindings: dma: marvell,mmp-dma: Add SpacemiT K1 PDMA support Guodong Xu
2025-07-01 5:36 ` [PATCH v2 2/8] dmaengine: mmp_pdma: Add optional clock support Guodong Xu
@ 2025-07-01 5:36 ` Guodong Xu
2025-07-01 5:36 ` [PATCH v2 4/8] dmaengine: mmp_pdma: Add operations structure for controller abstraction Guodong Xu
` (4 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: Guodong Xu @ 2025-07-01 5:36 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Duje Mihanović, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: Alex Elder, Vivian Wang, dmaengine, devicetree, linux-kernel,
linux-riscv, spacemit, Guodong Xu
Add support to acquire and deassert an optional hardware reset controller
during mmp_pdma_probe().
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2: No change.
---
drivers/dma/mmp_pdma.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c
index 4a6dbf55823722d26cc69379d22aaa88fbe19313..fe627efeaff07436647f86ab5ec5333144a3c92d 100644
--- a/drivers/dma/mmp_pdma.c
+++ b/drivers/dma/mmp_pdma.c
@@ -16,6 +16,7 @@
#include <linux/platform_data/mmp_dma.h>
#include <linux/dmapool.h>
#include <linux/clk.h>
+#include <linux/reset.h>
#include <linux/of_dma.h>
#include <linux/of.h>
@@ -1021,6 +1022,7 @@ static int mmp_pdma_probe(struct platform_device *op)
struct mmp_pdma_device *pdev;
struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);
struct clk *clk;
+ struct reset_control *rst;
int i, ret, irq = 0;
int dma_channels = 0, irq_num = 0;
const enum dma_slave_buswidth widths =
@@ -1043,6 +1045,11 @@ static int mmp_pdma_probe(struct platform_device *op)
if (IS_ERR(clk))
return PTR_ERR(clk);
+ rst = devm_reset_control_get_optional_exclusive_deasserted(pdev->dev,
+ NULL);
+ if (IS_ERR(rst))
+ return PTR_ERR(rst);
+
if (pdev->dev->of_node) {
/* Parse new and deprecated dma-channels properties */
if (of_property_read_u32(pdev->dev->of_node, "dma-channels",
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 4/8] dmaengine: mmp_pdma: Add operations structure for controller abstraction
2025-07-01 5:36 [PATCH v2 0/8] dmaengine: mmp_pdma: Add SpacemiT K1 SoC support with 64-bit addressing Guodong Xu
` (2 preceding siblings ...)
2025-07-01 5:36 ` [PATCH v2 3/8] dmaengine: mmp_pdma: Add optional reset controller support Guodong Xu
@ 2025-07-01 5:36 ` Guodong Xu
2025-07-01 5:36 ` [PATCH v2 5/8] dmaengine: mmp_pdma: Add SpacemiT K1 PDMA support with 64-bit addressing Guodong Xu
` (3 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: Guodong Xu @ 2025-07-01 5:36 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Duje Mihanović, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: Alex Elder, Vivian Wang, dmaengine, devicetree, linux-kernel,
linux-riscv, spacemit, Guodong Xu
Introduce mmp_pdma_ops structure to abstract 32-bit addressing operations
and enable support for different controller variants. This prepares for
adding 64-bit addressing support.
The ops structure includes:
- Hardware register operations (read/write DDADR, DSADR, DTADR)
- Descriptor memory operations (manipulate descriptor structs)
- Controller configuration (run bits, DMA mask)
Convert existing 32-bit operations to use the new abstraction layer
while maintaining backward compatibility.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2: New patch, introduce mmp_pdma_ops for 32-bit addressing operations.
---
drivers/dma/mmp_pdma.c | 187 +++++++++++++++++++++++++++++++++++++++++--------
1 file changed, 156 insertions(+), 31 deletions(-)
diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c
index fe627efeaff07436647f86ab5ec5333144a3c92d..610df28f429783779c1c143a13b3a829e42cf003 100644
--- a/drivers/dma/mmp_pdma.c
+++ b/drivers/dma/mmp_pdma.c
@@ -25,7 +25,7 @@
#define DCSR 0x0000
#define DALGN 0x00a0
#define DINT 0x00f0
-#define DDADR 0x0200
+#define DDADR(n) (0x0200 + ((n) << 4))
#define DSADR(n) (0x0204 + ((n) << 4))
#define DTADR(n) (0x0208 + ((n) << 4))
#define DCMD 0x020c
@@ -120,12 +120,55 @@ struct mmp_pdma_phy {
struct mmp_pdma_chan *vchan;
};
+/**
+ * struct mmp_pdma_ops - Operations for the MMP PDMA controller
+ *
+ * Hardware Register Operations (read/write hardware registers):
+ * @write_next_addr: Function to program address of next descriptor into
+ * DDADR/DDADRH
+ * @read_src_addr: Function to read the source address from DSADR/DSADRH
+ * @read_dst_addr: Function to read the destination address from DTADR/DTADRH
+ *
+ * Descriptor Memory Operations (manipulate descriptor structs in memory):
+ * @set_desc_next_addr: Function to set next descriptor address in descriptor
+ * @set_desc_src_addr: Function to set the source address in descriptor
+ * @set_desc_dst_addr: Function to set the destination address in descriptor
+ * @get_desc_src_addr: Function to get the source address from descriptor
+ * @get_desc_dst_addr: Function to get the destination address from descriptor
+ *
+ * Controller Configuration:
+ * @run_bits: Control bits in DCSR register for channel start/stop
+ * @dma_mask: DMA addressing capability of controller. 0 to use OF/platform
+ * settings, or explicit mask like DMA_BIT_MASK(32/64)
+ */
+struct mmp_pdma_ops {
+ /* Hardware Register Operations */
+ void (*write_next_addr)(struct mmp_pdma_phy *phy, dma_addr_t addr);
+ u64 (*read_src_addr)(struct mmp_pdma_phy *phy);
+ u64 (*read_dst_addr)(struct mmp_pdma_phy *phy);
+
+ /* Descriptor Memory Operations */
+ void (*set_desc_next_addr)(struct mmp_pdma_desc_hw *desc,
+ dma_addr_t addr);
+ void (*set_desc_src_addr)(struct mmp_pdma_desc_hw *desc,
+ dma_addr_t addr);
+ void (*set_desc_dst_addr)(struct mmp_pdma_desc_hw *desc,
+ dma_addr_t addr);
+ u64 (*get_desc_src_addr)(const struct mmp_pdma_desc_hw *desc);
+ u64 (*get_desc_dst_addr)(const struct mmp_pdma_desc_hw *desc);
+
+ /* Controller Configuration */
+ u32 run_bits;
+ u64 dma_mask;
+};
+
struct mmp_pdma_device {
int dma_channels;
void __iomem *base;
struct device *dev;
struct dma_device device;
struct mmp_pdma_phy *phy;
+ const struct mmp_pdma_ops *ops;
spinlock_t phy_lock; /* protect alloc/free phy channels */
};
@@ -138,24 +181,61 @@ struct mmp_pdma_device {
#define to_mmp_pdma_dev(dmadev) \
container_of(dmadev, struct mmp_pdma_device, device)
-static int mmp_pdma_config_write(struct dma_chan *dchan,
- struct dma_slave_config *cfg,
- enum dma_transfer_direction direction);
+/* For 32-bit PDMA */
+static void write_next_addr_32(struct mmp_pdma_phy *phy, dma_addr_t addr)
+{
+ writel(addr, phy->base + DDADR(phy->idx));
+}
-static void set_desc(struct mmp_pdma_phy *phy, dma_addr_t addr)
+static u64 read_src_addr_32(struct mmp_pdma_phy *phy)
{
- u32 reg = (phy->idx << 4) + DDADR;
+ return readl(phy->base + DSADR(phy->idx));
+}
- writel(addr, phy->base + reg);
+static u64 read_dst_addr_32(struct mmp_pdma_phy *phy)
+{
+ return readl(phy->base + DTADR(phy->idx));
+}
+
+static void set_desc_next_addr_32(struct mmp_pdma_desc_hw *desc, dma_addr_t addr)
+{
+ desc->ddadr = addr;
+}
+
+static void set_desc_src_addr_32(struct mmp_pdma_desc_hw *desc, dma_addr_t addr)
+{
+ desc->dsadr = addr;
+}
+
+static void set_desc_dst_addr_32(struct mmp_pdma_desc_hw *desc, dma_addr_t addr)
+{
+ desc->dtadr = addr;
}
+static u64 get_desc_src_addr_32(const struct mmp_pdma_desc_hw *desc)
+{
+ return desc->dsadr;
+}
+
+static u64 get_desc_dst_addr_32(const struct mmp_pdma_desc_hw *desc)
+{
+ return desc->dtadr;
+}
+
+static int mmp_pdma_config_write(struct dma_chan *dchan,
+ struct dma_slave_config *cfg,
+ enum dma_transfer_direction direction);
+
static void enable_chan(struct mmp_pdma_phy *phy)
{
u32 reg, dalgn;
+ struct mmp_pdma_device *pdev;
if (!phy->vchan)
return;
+ pdev = to_mmp_pdma_dev(phy->vchan->chan.device);
+
reg = DRCMR(phy->vchan->drcmr);
writel(DRCMR_MAPVLD | phy->idx, phy->base + reg);
@@ -167,18 +247,29 @@ static void enable_chan(struct mmp_pdma_phy *phy)
writel(dalgn, phy->base + DALGN);
reg = (phy->idx << 2) + DCSR;
- writel(readl(phy->base + reg) | DCSR_RUN, phy->base + reg);
+ writel(readl(phy->base + reg) | pdev->ops->run_bits,
+ phy->base + reg);
}
static void disable_chan(struct mmp_pdma_phy *phy)
{
- u32 reg;
+ u32 reg, dcsr;
if (!phy)
return;
reg = (phy->idx << 2) + DCSR;
- writel(readl(phy->base + reg) & ~DCSR_RUN, phy->base + reg);
+ dcsr = readl(phy->base + reg);
+
+ if (phy->vchan) {
+ struct mmp_pdma_device *pdev;
+
+ pdev = to_mmp_pdma_dev(phy->vchan->chan.device);
+ writel(dcsr & ~pdev->ops->run_bits, phy->base + reg);
+ } else {
+ /* If no vchan, just clear the RUN bit */
+ writel(dcsr & ~DCSR_RUN, phy->base + reg);
+ }
}
static int clear_chan_irq(struct mmp_pdma_phy *phy)
@@ -297,6 +388,7 @@ static void mmp_pdma_free_phy(struct mmp_pdma_chan *pchan)
static void start_pending_queue(struct mmp_pdma_chan *chan)
{
struct mmp_pdma_desc_sw *desc;
+ struct mmp_pdma_device *pdev = to_mmp_pdma_dev(chan->chan.device);
/* still in running, irq will start the pending list */
if (!chan->idle) {
@@ -331,7 +423,7 @@ static void start_pending_queue(struct mmp_pdma_chan *chan)
* Program the descriptor's address into the DMA controller,
* then start the DMA transaction
*/
- set_desc(chan->phy, desc->async_tx.phys);
+ pdev->ops->write_next_addr(chan->phy, desc->async_tx.phys);
enable_chan(chan->phy);
chan->idle = false;
}
@@ -447,6 +539,7 @@ mmp_pdma_prep_memcpy(struct dma_chan *dchan,
size_t len, unsigned long flags)
{
struct mmp_pdma_chan *chan;
+ struct mmp_pdma_device *pdev = to_mmp_pdma_dev(dchan->device);
struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new;
size_t copy = 0;
@@ -478,13 +571,14 @@ mmp_pdma_prep_memcpy(struct dma_chan *dchan,
chan->byte_align = true;
new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & copy);
- new->desc.dsadr = dma_src;
- new->desc.dtadr = dma_dst;
+ pdev->ops->set_desc_src_addr(&new->desc, dma_src);
+ pdev->ops->set_desc_dst_addr(&new->desc, dma_dst);
if (!first)
first = new;
else
- prev->desc.ddadr = new->async_tx.phys;
+ pdev->ops->set_desc_next_addr(&prev->desc,
+ new->async_tx.phys);
new->async_tx.cookie = 0;
async_tx_ack(&new->async_tx);
@@ -528,6 +622,7 @@ mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
unsigned long flags, void *context)
{
struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+ struct mmp_pdma_device *pdev = to_mmp_pdma_dev(dchan->device);
struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new = NULL;
size_t len, avail;
struct scatterlist *sg;
@@ -559,17 +654,18 @@ mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & len);
if (dir == DMA_MEM_TO_DEV) {
- new->desc.dsadr = addr;
+ pdev->ops->set_desc_src_addr(&new->desc, addr);
new->desc.dtadr = chan->dev_addr;
} else {
new->desc.dsadr = chan->dev_addr;
- new->desc.dtadr = addr;
+ pdev->ops->set_desc_dst_addr(&new->desc, addr);
}
if (!first)
first = new;
else
- prev->desc.ddadr = new->async_tx.phys;
+ pdev->ops->set_desc_next_addr(&prev->desc,
+ new->async_tx.phys);
new->async_tx.cookie = 0;
async_tx_ack(&new->async_tx);
@@ -609,6 +705,7 @@ mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan,
unsigned long flags)
{
struct mmp_pdma_chan *chan;
+ struct mmp_pdma_device *pdev = to_mmp_pdma_dev(dchan->device);
struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new;
dma_addr_t dma_src, dma_dst;
@@ -651,13 +748,14 @@ mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan,
new->desc.dcmd = (chan->dcmd | DCMD_ENDIRQEN |
(DCMD_LENGTH & period_len));
- new->desc.dsadr = dma_src;
- new->desc.dtadr = dma_dst;
+ pdev->ops->set_desc_src_addr(&new->desc, dma_src);
+ pdev->ops->set_desc_dst_addr(&new->desc, dma_dst);
if (!first)
first = new;
else
- prev->desc.ddadr = new->async_tx.phys;
+ pdev->ops->set_desc_next_addr(&prev->desc,
+ new->async_tx.phys);
new->async_tx.cookie = 0;
async_tx_ack(&new->async_tx);
@@ -678,7 +776,7 @@ mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan,
first->async_tx.cookie = -EBUSY;
/* make the cyclic link */
- new->desc.ddadr = first->async_tx.phys;
+ pdev->ops->set_desc_next_addr(&new->desc, first->async_tx.phys);
chan->cyclic_first = first;
return &first->async_tx;
@@ -764,7 +862,9 @@ static unsigned int mmp_pdma_residue(struct mmp_pdma_chan *chan,
dma_cookie_t cookie)
{
struct mmp_pdma_desc_sw *sw;
- u32 curr, residue = 0;
+ struct mmp_pdma_device *pdev = to_mmp_pdma_dev(chan->chan.device);
+ u64 curr;
+ u32 residue = 0;
bool passed = false;
bool cyclic = chan->cyclic_first != NULL;
@@ -776,17 +876,18 @@ static unsigned int mmp_pdma_residue(struct mmp_pdma_chan *chan,
return 0;
if (chan->dir == DMA_DEV_TO_MEM)
- curr = readl(chan->phy->base + DTADR(chan->phy->idx));
+ curr = pdev->ops->read_dst_addr(chan->phy);
else
- curr = readl(chan->phy->base + DSADR(chan->phy->idx));
+ curr = pdev->ops->read_src_addr(chan->phy);
list_for_each_entry(sw, &chan->chain_running, node) {
- u32 start, end, len;
+ u64 start, end;
+ u32 len;
if (chan->dir == DMA_DEV_TO_MEM)
- start = sw->desc.dtadr;
+ start = pdev->ops->get_desc_dst_addr(&sw->desc);
else
- start = sw->desc.dsadr;
+ start = pdev->ops->get_desc_src_addr(&sw->desc);
len = sw->desc.dcmd & DCMD_LENGTH;
end = start + len;
@@ -802,7 +903,7 @@ static unsigned int mmp_pdma_residue(struct mmp_pdma_chan *chan,
if (passed) {
residue += len;
} else if (curr >= start && curr <= end) {
- residue += end - curr;
+ residue += (u32)(end - curr);
passed = true;
}
@@ -996,9 +1097,26 @@ static int mmp_pdma_chan_init(struct mmp_pdma_device *pdev, int idx, int irq)
return 0;
}
+static const struct mmp_pdma_ops marvell_pdma_v1_ops = {
+ .write_next_addr = write_next_addr_32,
+ .read_src_addr = read_src_addr_32,
+ .read_dst_addr = read_dst_addr_32,
+ .set_desc_next_addr = set_desc_next_addr_32,
+ .set_desc_src_addr = set_desc_src_addr_32,
+ .set_desc_dst_addr = set_desc_dst_addr_32,
+ .get_desc_src_addr = get_desc_src_addr_32,
+ .get_desc_dst_addr = get_desc_dst_addr_32,
+ .run_bits = (DCSR_RUN),
+ .dma_mask = 0, /* let OF/platform set DMA mask */
+};
+
static const struct of_device_id mmp_pdma_dt_ids[] = {
- { .compatible = "marvell,pdma-1.0", },
- {}
+ {
+ .compatible = "marvell,pdma-1.0",
+ .data = &marvell_pdma_v1_ops
+ }, {
+ /* sentinel */
+ }
};
MODULE_DEVICE_TABLE(of, mmp_pdma_dt_ids);
@@ -1050,6 +1168,10 @@ static int mmp_pdma_probe(struct platform_device *op)
if (IS_ERR(rst))
return PTR_ERR(rst);
+ pdev->ops = of_device_get_match_data(&op->dev);
+ if (!pdev->ops)
+ return -ENODEV;
+
if (pdev->dev->of_node) {
/* Parse new and deprecated dma-channels properties */
if (of_property_read_u32(pdev->dev->of_node, "dma-channels",
@@ -1111,7 +1233,10 @@ static int mmp_pdma_probe(struct platform_device *op)
pdev->device.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
pdev->device.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
- if (pdev->dev->coherent_dma_mask)
+ /* Set DMA mask based on ops->dma_mask, or OF/platform */
+ if (pdev->ops->dma_mask)
+ dma_set_mask(pdev->dev, pdev->ops->dma_mask);
+ else if (pdev->dev->coherent_dma_mask)
dma_set_mask(pdev->dev, pdev->dev->coherent_dma_mask);
else
dma_set_mask(pdev->dev, DMA_BIT_MASK(64));
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 5/8] dmaengine: mmp_pdma: Add SpacemiT K1 PDMA support with 64-bit addressing
2025-07-01 5:36 [PATCH v2 0/8] dmaengine: mmp_pdma: Add SpacemiT K1 SoC support with 64-bit addressing Guodong Xu
` (3 preceding siblings ...)
2025-07-01 5:36 ` [PATCH v2 4/8] dmaengine: mmp_pdma: Add operations structure for controller abstraction Guodong Xu
@ 2025-07-01 5:36 ` Guodong Xu
2025-07-01 5:37 ` [PATCH v2 6/8] riscv: dts: spacemit: Add PDMA0 node for K1 SoC Guodong Xu
` (2 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: Guodong Xu @ 2025-07-01 5:36 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Duje Mihanović, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: Alex Elder, Vivian Wang, dmaengine, devicetree, linux-kernel,
linux-riscv, spacemit, Guodong Xu
Add support for SpacemiT K1 PDMA controller which features 64-bit
addressing capabilities.
The SpacemiT K1 PDMA extends the descriptor format with additional
32-bit words for high address bits, enabling access to memory beyond
4GB boundaries. The new spacemit_k1_pdma_ops provides necessary 64-bit
address handling functions and k1 specific controller configurations.
Key changes:
- Add ARCH_SPACEMIT dependency to Kconfig
- Define new high 32-bit address registers (DDADRH, DSADRH, DTADRH)
- Add DCSR_LPAEEN bit for Long Physical Address Extension Enable
- Implement 64-bit operations for SpacemiT K1 PDMA
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2: New patch.
- Implement 64-bit addrssing support to mmp_pdma
- Add support for SpacemiT K1 PDMA
- Extend the MMP_PDMA entry in Kconfig to depend on ARCH_SPACEMIT
---
drivers/dma/Kconfig | 2 +-
drivers/dma/mmp_pdma.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 82 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index db87dd2a07f7606e40dc26ea41d26fcdd1fad979..fff70f66c773934efb2fcafdc3628ba06c734640 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -451,7 +451,7 @@ config MILBEAUT_XDMAC
config MMP_PDMA
tristate "MMP PDMA support"
- depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
+ depends on ARCH_MMP || ARCH_PXA || ARCH_SPACEMIT || COMPILE_TEST
select DMA_ENGINE
help
Support the MMP PDMA engine for PXA and MMP platform.
diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c
index 610df28f429783779c1c143a13b3a829e42cf003..28c03d05e0b2708fcb8faffeeb97b97ed6fcbdc5 100644
--- a/drivers/dma/mmp_pdma.c
+++ b/drivers/dma/mmp_pdma.c
@@ -28,6 +28,9 @@
#define DDADR(n) (0x0200 + ((n) << 4))
#define DSADR(n) (0x0204 + ((n) << 4))
#define DTADR(n) (0x0208 + ((n) << 4))
+#define DDADRH(n) (0x0300 + ((n) << 4))
+#define DSADRH(n) (0x0304 + ((n) << 4))
+#define DTADRH(n) (0x0308 + ((n) << 4))
#define DCMD 0x020c
#define DCSR_RUN BIT(31) /* Run Bit (read / write) */
@@ -44,6 +47,7 @@
#define DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */
#define DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */
#define DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */
+#define DCSR_LPAEEN BIT(21) /* Long Physical Address Extension Enable */
#define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */
#define DCSR_EORINTR BIT(9) /* The end of Receive */
@@ -76,6 +80,16 @@ struct mmp_pdma_desc_hw {
u32 dsadr; /* DSADR value for the current transfer */
u32 dtadr; /* DTADR value for the current transfer */
u32 dcmd; /* DCMD value for the current transfer */
+ /*
+ * The following 32-bit words are only used in the 64-bit, ie.
+ * LPAE (Long Physical Address Extension) mode.
+ * They are used to specify the high 32 bits of the descriptor's
+ * addresses.
+ */
+ u32 ddadrh; /* High 32-bit of DDADR */
+ u32 dsadrh; /* High 32-bit of DSADR */
+ u32 dtadrh; /* High 32-bit of DTADR */
+ u32 rsvd; /* reserved */
} __aligned(32);
struct mmp_pdma_desc_sw {
@@ -222,6 +236,57 @@ static u64 get_desc_dst_addr_32(const struct mmp_pdma_desc_hw *desc)
return desc->dtadr;
}
+/* For 64-bit PDMA */
+static void write_next_addr_64(struct mmp_pdma_phy *phy, dma_addr_t addr)
+{
+ writel(lower_32_bits(addr), phy->base + DDADR(phy->idx));
+ writel(upper_32_bits(addr), phy->base + DDADRH(phy->idx));
+}
+
+static u64 read_src_addr_64(struct mmp_pdma_phy *phy)
+{
+ u32 low = readl(phy->base + DSADR(phy->idx));
+ u32 high = readl(phy->base + DSADRH(phy->idx));
+
+ return ((u64)high << 32) | low;
+}
+
+static u64 read_dst_addr_64(struct mmp_pdma_phy *phy)
+{
+ u32 low = readl(phy->base + DTADR(phy->idx));
+ u32 high = readl(phy->base + DTADRH(phy->idx));
+
+ return ((u64)high << 32) | low;
+}
+
+static void set_desc_next_addr_64(struct mmp_pdma_desc_hw *desc, dma_addr_t addr)
+{
+ desc->ddadr = lower_32_bits(addr);
+ desc->ddadrh = upper_32_bits(addr);
+}
+
+static void set_desc_src_addr_64(struct mmp_pdma_desc_hw *desc, dma_addr_t addr)
+{
+ desc->dsadr = lower_32_bits(addr);
+ desc->dsadrh = upper_32_bits(addr);
+}
+
+static void set_desc_dst_addr_64(struct mmp_pdma_desc_hw *desc, dma_addr_t addr)
+{
+ desc->dtadr = lower_32_bits(addr);
+ desc->dtadrh = upper_32_bits(addr);
+}
+
+static u64 get_desc_src_addr_64(const struct mmp_pdma_desc_hw *desc)
+{
+ return ((u64)desc->dsadrh << 32) | desc->dsadr;
+}
+
+static u64 get_desc_dst_addr_64(const struct mmp_pdma_desc_hw *desc)
+{
+ return ((u64)desc->dtadrh << 32) | desc->dtadr;
+}
+
static int mmp_pdma_config_write(struct dma_chan *dchan,
struct dma_slave_config *cfg,
enum dma_transfer_direction direction);
@@ -1110,10 +1175,26 @@ static const struct mmp_pdma_ops marvell_pdma_v1_ops = {
.dma_mask = 0, /* let OF/platform set DMA mask */
};
+static const struct mmp_pdma_ops spacemit_k1_pdma_ops = {
+ .write_next_addr = write_next_addr_64,
+ .read_src_addr = read_src_addr_64,
+ .read_dst_addr = read_dst_addr_64,
+ .set_desc_next_addr = set_desc_next_addr_64,
+ .set_desc_src_addr = set_desc_src_addr_64,
+ .set_desc_dst_addr = set_desc_dst_addr_64,
+ .get_desc_src_addr = get_desc_src_addr_64,
+ .get_desc_dst_addr = get_desc_dst_addr_64,
+ .run_bits = (DCSR_RUN | DCSR_LPAEEN),
+ .dma_mask = DMA_BIT_MASK(64), /* force 64-bit DMA addr capability */
+};
+
static const struct of_device_id mmp_pdma_dt_ids[] = {
{
.compatible = "marvell,pdma-1.0",
.data = &marvell_pdma_v1_ops
+ }, {
+ .compatible = "spacemit,k1-pdma",
+ .data = &spacemit_k1_pdma_ops
}, {
/* sentinel */
}
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 6/8] riscv: dts: spacemit: Add PDMA0 node for K1 SoC
2025-07-01 5:36 [PATCH v2 0/8] dmaengine: mmp_pdma: Add SpacemiT K1 SoC support with 64-bit addressing Guodong Xu
` (4 preceding siblings ...)
2025-07-01 5:36 ` [PATCH v2 5/8] dmaengine: mmp_pdma: Add SpacemiT K1 PDMA support with 64-bit addressing Guodong Xu
@ 2025-07-01 5:37 ` Guodong Xu
2025-07-01 7:37 ` Krzysztof Kozlowski
2025-07-01 5:37 ` [PATCH v2 7/8] riscv: dts: spacemit: Enable PDMA0 on Banana Pi F3 and Milkv Jupiter Guodong Xu
2025-07-01 5:37 ` [PATCH v2 8/8] riscv: defconfig: Enable MMP_PDMA support for SpacemiT K1 SoC Guodong Xu
7 siblings, 1 reply; 18+ messages in thread
From: Guodong Xu @ 2025-07-01 5:37 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Duje Mihanović, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: Alex Elder, Vivian Wang, dmaengine, devicetree, linux-kernel,
linux-riscv, spacemit, Guodong Xu
Add PDMA0 dma-controller node under dma_bus for SpacemiT K1 SoC.
The PDMA0 node is marked as disabled by default, allowing board-specific
device trees to enable it as needed.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2:
- Updated the compatible string.
- Rebased. Part of the changes in v1 is now in this patchset:
- "riscv: dts: spacemit: Add DMA translation buses for K1"
- Link: https://lore.kernel.org/all/20250623-k1-dma-buses-rfc-wip-v1-0-c0144082061f@iscas.ac.cn/
---
arch/riscv/boot/dts/spacemit/k1.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 8f44c1458123be9e74a80878517b2b785d743bef..69e0b1edf3276df26c07c15d81607f83de0e5d57 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -591,6 +591,17 @@ uart9: serial@d4017800 {
status = "disabled";
};
+ pdma0: dma-controller@d4000000 {
+ compatible = "spacemit,k1-pdma";
+ reg = <0x0 0xd4000000 0x0 0x4000>;
+ interrupts = <72>;
+ clocks = <&syscon_apmu CLK_DMA>;
+ resets = <&syscon_apmu RESET_DMA>;
+ #dma-cells= <2>;
+ #dma-channels = <16>;
+ status = "disabled";
+ };
+
sec_uart1: serial@f0612000 {
compatible = "spacemit,k1-uart",
"intel,xscale-uart";
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v2 6/8] riscv: dts: spacemit: Add PDMA0 node for K1 SoC
2025-07-01 5:37 ` [PATCH v2 6/8] riscv: dts: spacemit: Add PDMA0 node for K1 SoC Guodong Xu
@ 2025-07-01 7:37 ` Krzysztof Kozlowski
2025-07-01 8:19 ` Guodong Xu
0 siblings, 1 reply; 18+ messages in thread
From: Krzysztof Kozlowski @ 2025-07-01 7:37 UTC (permalink / raw)
To: Guodong Xu, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Duje Mihanović, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: Alex Elder, Vivian Wang, dmaengine, devicetree, linux-kernel,
linux-riscv, spacemit
On 01/07/2025 07:37, Guodong Xu wrote:
> Add PDMA0 dma-controller node under dma_bus for SpacemiT K1 SoC.
>
> The PDMA0 node is marked as disabled by default, allowing board-specific
> device trees to enable it as needed.
>
> Signed-off-by: Guodong Xu <guodong@riscstar.com>
> ---
> v2:
> - Updated the compatible string.
> - Rebased. Part of the changes in v1 is now in this patchset:
> - "riscv: dts: spacemit: Add DMA translation buses for K1"
> - Link: https://lore.kernel.org/all/20250623-k1-dma-buses-rfc-wip-v1-0-c0144082061f@iscas.ac.cn/
> ---
> arch/riscv/boot/dts/spacemit/k1.dtsi | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> index 8f44c1458123be9e74a80878517b2b785d743bef..69e0b1edf3276df26c07c15d81607f83de0e5d57 100644
> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -591,6 +591,17 @@ uart9: serial@d4017800 {
> status = "disabled";
> };
>
> + pdma0: dma-controller@d4000000 {
Oddly placed. Is spacemit not following standard DTS coding style ordering?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v2 6/8] riscv: dts: spacemit: Add PDMA0 node for K1 SoC
2025-07-01 7:37 ` Krzysztof Kozlowski
@ 2025-07-01 8:19 ` Guodong Xu
0 siblings, 0 replies; 18+ messages in thread
From: Guodong Xu @ 2025-07-01 8:19 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Duje Mihanović, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Alex Elder,
Vivian Wang, dmaengine, devicetree, linux-kernel, linux-riscv,
spacemit
On Tue, Jul 1, 2025 at 3:37 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 01/07/2025 07:37, Guodong Xu wrote:
> > Add PDMA0 dma-controller node under dma_bus for SpacemiT K1 SoC.
> >
> > The PDMA0 node is marked as disabled by default, allowing board-specific
> > device trees to enable it as needed.
> >
> > Signed-off-by: Guodong Xu <guodong@riscstar.com>
> > ---
> > v2:
> > - Updated the compatible string.
> > - Rebased. Part of the changes in v1 is now in this patchset:
> > - "riscv: dts: spacemit: Add DMA translation buses for K1"
> > - Link: https://lore.kernel.org/all/20250623-k1-dma-buses-rfc-wip-v1-0-c0144082061f@iscas.ac.cn/
> > ---
> > arch/riscv/boot/dts/spacemit/k1.dtsi | 11 +++++++++++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > index 8f44c1458123be9e74a80878517b2b785d743bef..69e0b1edf3276df26c07c15d81607f83de0e5d57 100644
> > --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > @@ -591,6 +591,17 @@ uart9: serial@d4017800 {
> > status = "disabled";
> > };
> >
> > + pdma0: dma-controller@d4000000 {
>
>
> Oddly placed. Is spacemit not following standard DTS coding style ordering?
>
Oh, I see the issue. I will fix this by ordering by "unit address in
ascending order". Thanks for pointing this out.
-Guodong
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 7/8] riscv: dts: spacemit: Enable PDMA0 on Banana Pi F3 and Milkv Jupiter
2025-07-01 5:36 [PATCH v2 0/8] dmaengine: mmp_pdma: Add SpacemiT K1 SoC support with 64-bit addressing Guodong Xu
` (5 preceding siblings ...)
2025-07-01 5:37 ` [PATCH v2 6/8] riscv: dts: spacemit: Add PDMA0 node for K1 SoC Guodong Xu
@ 2025-07-01 5:37 ` Guodong Xu
2025-07-01 7:36 ` Krzysztof Kozlowski
2025-07-01 5:37 ` [PATCH v2 8/8] riscv: defconfig: Enable MMP_PDMA support for SpacemiT K1 SoC Guodong Xu
7 siblings, 1 reply; 18+ messages in thread
From: Guodong Xu @ 2025-07-01 5:37 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Duje Mihanović, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: Alex Elder, Vivian Wang, dmaengine, devicetree, linux-kernel,
linux-riscv, spacemit, Guodong Xu
Enable the PDMA0 on the SpacemiT K1-based Banana Pi F3 and Milkv Jupiter
boards by setting its status to "okay".
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2: added pdma0 enablement on Milkv Jupiter
---
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 ++++
arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index fe22c747c5012fe56d42ac8a7efdbbdb694f31b6..39133450e07f2cb9cb2247dc0284851f8c55031b 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -45,3 +45,7 @@ &uart0 {
pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
+
+&pdma0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
index 4483192141049caa201c093fb206b6134a064f42..afb88ddf36eb8e5e3bf74fa29f9bc006e45814e7 100644
--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
@@ -25,3 +25,7 @@ &uart0 {
pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
+
+&pdma0 {
+ status = "okay";
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v2 7/8] riscv: dts: spacemit: Enable PDMA0 on Banana Pi F3 and Milkv Jupiter
2025-07-01 5:37 ` [PATCH v2 7/8] riscv: dts: spacemit: Enable PDMA0 on Banana Pi F3 and Milkv Jupiter Guodong Xu
@ 2025-07-01 7:36 ` Krzysztof Kozlowski
2025-07-01 8:48 ` Guodong Xu
0 siblings, 1 reply; 18+ messages in thread
From: Krzysztof Kozlowski @ 2025-07-01 7:36 UTC (permalink / raw)
To: Guodong Xu, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Duje Mihanović, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: Alex Elder, Vivian Wang, dmaengine, devicetree, linux-kernel,
linux-riscv, spacemit
On 01/07/2025 07:37, Guodong Xu wrote:
> Enable the PDMA0 on the SpacemiT K1-based Banana Pi F3 and Milkv Jupiter
> boards by setting its status to "okay".
>
> Signed-off-by: Guodong Xu <guodong@riscstar.com>
> ---
> v2: added pdma0 enablement on Milkv Jupiter
> ---
> arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 ++++
> arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 4 ++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> index fe22c747c5012fe56d42ac8a7efdbbdb694f31b6..39133450e07f2cb9cb2247dc0284851f8c55031b 100644
> --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> @@ -45,3 +45,7 @@ &uart0 {
> pinctrl-0 = <&uart0_2_cfg>;
> status = "okay";
> };
> +
> +&pdma0 {
Does not look like placed according to DTS coding style. What sort of
ordering Spacemit follows?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v2 7/8] riscv: dts: spacemit: Enable PDMA0 on Banana Pi F3 and Milkv Jupiter
2025-07-01 7:36 ` Krzysztof Kozlowski
@ 2025-07-01 8:48 ` Guodong Xu
2025-07-01 9:02 ` Krzysztof Kozlowski
0 siblings, 1 reply; 18+ messages in thread
From: Guodong Xu @ 2025-07-01 8:48 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Duje Mihanović, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Alex Elder,
Vivian Wang, dmaengine, devicetree, linux-kernel, linux-riscv,
spacemit
On Tue, Jul 1, 2025 at 3:36 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 01/07/2025 07:37, Guodong Xu wrote:
> > Enable the PDMA0 on the SpacemiT K1-based Banana Pi F3 and Milkv Jupiter
> > boards by setting its status to "okay".
> >
> > Signed-off-by: Guodong Xu <guodong@riscstar.com>
> > ---
> > v2: added pdma0 enablement on Milkv Jupiter
> > ---
> > arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 ++++
> > arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 4 ++++
> > 2 files changed, 8 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> > index fe22c747c5012fe56d42ac8a7efdbbdb694f31b6..39133450e07f2cb9cb2247dc0284851f8c55031b 100644
> > --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> > +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> > @@ -45,3 +45,7 @@ &uart0 {
> > pinctrl-0 = <&uart0_2_cfg>;
> > status = "okay";
> > };
> > +
> > +&pdma0 {
>
>
> Does not look like placed according to DTS coding style. What sort of
> ordering Spacemit follows?
>
Agreed. We should establish a consistent ordering rule for SpacemiT board
DTS files. According to the coding style documentation, there are two
acceptable approaches for ordering node references in board DTS files:
"When extending nodes in the board DTS via &label, the entries shall be
ordered either alpha-numerically or by keeping the order from DTSI, where
the choice depends on the subarchitecture."
Refer to Documentation/devicetree/bindings/dts-coding-style.rst
My preference would be alphabetical ordering for easy maintainability. However,
I'd like to hear Yixun's perspective on this before we standardize the
approach across both board DTS files, BPI-F3 and MilkV Juptier.
Thanks.
Guodong
>
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v2 7/8] riscv: dts: spacemit: Enable PDMA0 on Banana Pi F3 and Milkv Jupiter
2025-07-01 8:48 ` Guodong Xu
@ 2025-07-01 9:02 ` Krzysztof Kozlowski
2025-07-01 10:04 ` Guodong Xu
0 siblings, 1 reply; 18+ messages in thread
From: Krzysztof Kozlowski @ 2025-07-01 9:02 UTC (permalink / raw)
To: Guodong Xu
Cc: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Duje Mihanović, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Alex Elder,
Vivian Wang, dmaengine, devicetree, linux-kernel, linux-riscv,
spacemit
On 01/07/2025 10:48, Guodong Xu wrote:
> On Tue, Jul 1, 2025 at 3:36 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>> On 01/07/2025 07:37, Guodong Xu wrote:
>>> Enable the PDMA0 on the SpacemiT K1-based Banana Pi F3 and Milkv Jupiter
>>> boards by setting its status to "okay".
>>>
>>> Signed-off-by: Guodong Xu <guodong@riscstar.com>
>>> ---
>>> v2: added pdma0 enablement on Milkv Jupiter
>>> ---
>>> arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 ++++
>>> arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 4 ++++
>>> 2 files changed, 8 insertions(+)
>>>
>>> diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
>>> index fe22c747c5012fe56d42ac8a7efdbbdb694f31b6..39133450e07f2cb9cb2247dc0284851f8c55031b 100644
>>> --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
>>> +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
>>> @@ -45,3 +45,7 @@ &uart0 {
>>> pinctrl-0 = <&uart0_2_cfg>;
>>> status = "okay";
>>> };
>>> +
>>> +&pdma0 {
>>
>>
>> Does not look like placed according to DTS coding style. What sort of
>> ordering Spacemit follows?
>>
>
> Agreed. We should establish a consistent ordering rule for SpacemiT board
Isn't there a style already? Or what is the style for Risc-v arch?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v2 7/8] riscv: dts: spacemit: Enable PDMA0 on Banana Pi F3 and Milkv Jupiter
2025-07-01 9:02 ` Krzysztof Kozlowski
@ 2025-07-01 10:04 ` Guodong Xu
0 siblings, 0 replies; 18+ messages in thread
From: Guodong Xu @ 2025-07-01 10:04 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Duje Mihanović, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Alex Elder,
Vivian Wang, dmaengine, devicetree, linux-kernel, linux-riscv,
spacemit
On Tue, Jul 1, 2025 at 5:02 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 01/07/2025 10:48, Guodong Xu wrote:
> > On Tue, Jul 1, 2025 at 3:36 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >>
> >> On 01/07/2025 07:37, Guodong Xu wrote:
> >>> Enable the PDMA0 on the SpacemiT K1-based Banana Pi F3 and Milkv Jupiter
> >>> boards by setting its status to "okay".
> >>>
> >>> Signed-off-by: Guodong Xu <guodong@riscstar.com>
> >>> ---
> >>> v2: added pdma0 enablement on Milkv Jupiter
> >>> ---
> >>> arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 ++++
> >>> arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 4 ++++
> >>> 2 files changed, 8 insertions(+)
> >>>
> >>> diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> >>> index fe22c747c5012fe56d42ac8a7efdbbdb694f31b6..39133450e07f2cb9cb2247dc0284851f8c55031b 100644
> >>> --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> >>> +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> >>> @@ -45,3 +45,7 @@ &uart0 {
> >>> pinctrl-0 = <&uart0_2_cfg>;
> >>> status = "okay";
> >>> };
> >>> +
> >>> +&pdma0 {
> >>
> >>
> >> Does not look like placed according to DTS coding style. What sort of
> >> ordering Spacemit follows?
> >>
> >
> > Agreed. We should establish a consistent ordering rule for SpacemiT board
>
>
> Isn't there a style already? Or what is the style for Risc-v arch?
>
Per my checking, it's not consistent for arch/riscv.
SiFive boards (hifive-unleashed-a00.dts and
hifive-unmatched-a00.dts) are not alphabetical.
Most other RISC-V vendors (StarFive, Microchip, Sophgo Milk-V Duo, etc.)
use alphabetical ordering. That's the majority. Right?
-Guodong
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 8/8] riscv: defconfig: Enable MMP_PDMA support for SpacemiT K1 SoC
2025-07-01 5:36 [PATCH v2 0/8] dmaengine: mmp_pdma: Add SpacemiT K1 SoC support with 64-bit addressing Guodong Xu
` (6 preceding siblings ...)
2025-07-01 5:37 ` [PATCH v2 7/8] riscv: dts: spacemit: Enable PDMA0 on Banana Pi F3 and Milkv Jupiter Guodong Xu
@ 2025-07-01 5:37 ` Guodong Xu
7 siblings, 0 replies; 18+ messages in thread
From: Guodong Xu @ 2025-07-01 5:37 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Yixun Lan, Duje Mihanović, Philipp Zabel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: Alex Elder, Vivian Wang, dmaengine, devicetree, linux-kernel,
linux-riscv, spacemit, Guodong Xu
Enable CONFIG_MMP_PDMA in the riscv defconfig for SpacemiT K1 SoC boards.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2: Rebased. Part of the modification in v1 is now in this patch:
- "riscv: defconfig: run savedefconfig to reorder it"
, which has been merged into riscv/linux.git (for-next)
- Link: https://git.kernel.org/riscv/c/d958097bdf88
---
arch/riscv/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 37c98c0f98ffc0ee9d021e4d07aa37a27d342f7a..b6519fcc91c0bb56f71df336fd3793af3d64fe78 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -240,6 +240,7 @@ CONFIG_RTC_DRV_SUN6I=y
CONFIG_DMADEVICES=y
CONFIG_DMA_SUN6I=m
CONFIG_DW_AXI_DMAC=y
+CONFIG_MMP_PDMA=m
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_INPUT=y
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread