From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v1] dmaengine: tegra: Use relaxed versions of readl/writel From: Jon Hunter Message-Id: Date: Fri, 26 Apr 2019 10:52:15 +0100 To: Dmitry Osipenko , Laxman Dewangan , Vinod Koul , Thierry Reding Cc: dmaengine@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org List-ID: T24gMjUvMDQvMjAxOSAwMDoxNywgRG1pdHJ5IE9zaXBlbmtvIHdyb3RlOgo+IFRoZSByZWFkbC93 cml0ZWwgZnVuY3Rpb25zIGFyZSBpbnNlcnRpbmcgbWVtb3J5IGJhcnJpZXIgaW4gb3JkZXIgdG8K PiBlbnN1cmUgdGhhdCBtZW1vcnkgc3RvcmVzIGFyZSBjb21wbGV0ZWQuIE9uIFRlZ3JhMjAgYW5k IFRlZ3JhMzAgdGhpcwo+IHJlc3VsdHMgaW4gTDIgY2FjaGUgc3luY2luZyB3aGljaCBpc24ndCBh IGNoZWFwZXN0IG9wZXJhdGlvbi4gVGhlCj4gdGVncmEyMC1hcGItZG1hIGRyaXZlciBkb2Vzbid0 IG5lZWQgdG8gc3luY2hyb25pemUgZ2VuZXJpYyBtZW1vcnkKPiBhY2Nlc3NlcywgaGVuY2UgdXNl IHRoZSByZWxheGVkIHZlcnNpb25zIG9mIHRoZSBmdW5jdGlvbnMuCgpEbyB5b3UgbWVhbiBkZXZp Y2UtaW8gYWNjZXNzZXMgaGVyZSBhcyB0aGlzIGlzIG5vdCBnZW5lcmljIG1lbW9yeT8KCkFsdGhv dWdoIHRoZXJlIG1heSBub3QgYmUgYW55IGlzc3VlcyB3aXRoIHRoaXMgY2hhbmdlLCBJIHRoaW5r IEkgbmVlZCBhCmJpdCBtb3JlIGNvbnZpbmNpbmcgdGhhdCB3ZSBzaG91bGQgZG8gdGhpcyBnaXZl biB0aGF0IHdlIGhhdmUgaGFkIGl0CnRoaXMgd2F5IGZvciBzb21ldGltZSBhbmQgSSB3b3VsZCBu b3QgbGlrZSB0byBzZWUgdXMgaW50cm9kdWNlIGFueQpyZWdyZXNzaW9ucyBhcyB0aGlzIHBvaW50 IHdpdGhvdXQgYmVpbmcgMTAwJSBjZXJ0YWluIHdlIHdvdWxkIG5vdC4KSWRlYWxseSwgaWYgSSBo YWQgc29tZSBnb29kIGV4dGVuc2l2ZSB0ZXN0cyBJIGNvdWxkIHJ1biB0byBoYW1tZXIgdGhlCkRN QSBmb3IgYWxsIGNvbmZpZ3VyYXRpb25zIHdpdGggZGlmZmVyZW50IGNvbWJpbmF0aW9ucyBvZiBj aGFubmVscwpydW5uaW5nIHNpbXVsdGFuZW91c2x5IHRoZW4gd2UgY291bGQgdGVzdCB0aGlzLCBi dXQgcmlnaHQgbm93IEkgZG9uJ3QgOi0oCgpIYXZlIHlvdSAuLi4KMS4gVGVzdGVkIGJvdGggY3lj bGljIGFuZCBzY2F0dGVyLWdhdGhlciB0cmFuc2ZlcnM/CjIuIFN0cmVzcyB0ZXN0ZWQgc2ltdWx0 YW5lb3VzIHRyYW5zZmVycyB3aXRoIHZhcmlvdXMgZGlmZmVyZW50CiAgIGNvbmZpZ3VyYXRpb25z PwozLiBRdWFudGlmaWVkIHRoZSBhY3R1YWwgcGVyZm9ybWFuY2UgYmVuZWZpdCBvZiB0aGlzIGNo YW5nZSBzbyB3ZSBjYW4KICAgdW5kZXJzdGFuZCBob3cgbXVjaCBvZiBhIHBlcmZvcm1hbmNlIGJv b3N0IHRoaXMgb2ZmZXJzPwoKQ2hlZXJzCkpvbgo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, T_DKIMWL_WL_HIGH autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25505C43218 for ; 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Fri, 26 Apr 2019 09:52:17 +0000 Subject: Re: [PATCH v1] dmaengine: tegra: Use relaxed versions of readl/writel To: Dmitry Osipenko , Laxman Dewangan , Vinod Koul , Thierry Reding CC: , , References: <20190424231708.21219-1-digetx@gmail.com> From: Jon Hunter Message-ID: Date: Fri, 26 Apr 2019 10:52:15 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190424231708.21219-1-digetx@gmail.com> X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="UTF-8" Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1556272345; bh=QOZLdR2lD8/lHPVcDQMaWidLRGULKACQlNQH2+6obcE=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=aZpKIHzM03vyqkp1zj3rvxPPJKNVuJZnSre0OhNHCSX5nHmutzs5LXO32h235RUc1 FNrk4ULuaLoOc/7pmjirYH0AajET9/aS+aDitcT8c2Rr12jtce2XdKE6/dlaz/Cw/E +rpQH6AcU9hRT5dSXBIlMRGRcO2g9ly3yaHjEjNRsmI9Ch8T9sApDqz0y5M/F4RmnS 0Ect3WQtONs017lRyaUtMlpawqKAknAwRITBhKVanQevtqeoSgBaLezRjE4u7cCmmg u2vUwuVguO+AasRwBuxg3G1z3elCb8UEHvCYiMTYcX+VQgmiV5JNwxwiMQ8tBRQzPt X73B6t83daEbQ== Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Message-ID: <20190426095215.0lMZRVR8-LGfg7llEI3RhpE2fBLpyRR4yWp8l_01g_c@z> On 25/04/2019 00:17, Dmitry Osipenko wrote: > The readl/writel functions are inserting memory barrier in order to > ensure that memory stores are completed. On Tegra20 and Tegra30 this > results in L2 cache syncing which isn't a cheapest operation. The > tegra20-apb-dma driver doesn't need to synchronize generic memory > accesses, hence use the relaxed versions of the functions. Do you mean device-io accesses here as this is not generic memory? Although there may not be any issues with this change, I think I need a bit more convincing that we should do this given that we have had it this way for sometime and I would not like to see us introduce any regressions as this point without being 100% certain we would not. Ideally, if I had some good extensive tests I could run to hammer the DMA for all configurations with different combinations of channels running simultaneously then we could test this, but right now I don't :-( Have you ... 1. Tested both cyclic and scatter-gather transfers? 2. Stress tested simultaneous transfers with various different configurations? 3. Quantified the actual performance benefit of this change so we can understand how much of a performance boost this offers? Cheers Jon