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Mon, 07 Sep 2026 09:14:42 -0700 (PDT) X-Received: by 2002:a17:903:1a28:b0:2db:31d5:1448 with SMTP id d9443c01a7336-2db31d514ebmr203963655ad.22.1788797682186; Mon, 07 Sep 2026 09:14:42 -0700 (PDT) Received: from [192.168.1.66] ([103.172.5.17]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3339bbf1feesm29345580eec.26.2026.09.07.09.14.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Sep 2026 09:14:41 -0700 (PDT) Message-ID: Date: Mon, 7 Sep 2026 21:44:38 +0530 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/2] i2c: Add I2C High-Speed mode support for qcom-geni To: Mukesh Savaliya , Vinod Koul , Frank Li , Viken Dadhaniya , Andi Shyti Cc: linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org References: <20260824-i2c-hs-v1-0-8dd94e5c6113@oss.qualcomm.com> <613960df-3d3d-445f-9533-57257eb5099b@oss.qualcomm.com> Content-Language: en-US From: Jyothi Kumar Seerapu In-Reply-To: <613960df-3d3d-445f-9533-57257eb5099b@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: 24g1BilCVqV3lXwj9Y0SQiVgxNJaiJBn X-Authority-Analysis: v=2.4 cv=U+aiy+ru c=1 sm=1 tr=0 ts=6a9ee2f3 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=tPI8lZtLbYv5uT6OEmdSlg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=PAEdTZexspgVwDamPmIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: 24g1BilCVqV3lXwj9Y0SQiVgxNJaiJBn X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA3MDE4MCBTYWx0ZWRfX+i/eLlIB1x3y O85MfoNged9r9x3GO8h6kCR21DRZBQAYUuDFgyxj6uoSazaqIiIHme1X6VR1fmOwjKSp81yrFIb q/hQoPLv5SIzNsx6K3vtX3LxMg26Fi0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA3MDE4MCBTYWx0ZWRfXyjiDbbSv9fU6 ngdeh7kkOX3SZzYBdjy/H1myzODkagBn/UYhalEfGcFSjH0Rg0KOpzJc8GXTVkrhRyLo2Q6cDeX tfkP6Jv85BzdLS2HQ8ewfznjnIDAHbjMHVRBpzFnHd2DQksulduIUNeMgZuciz6stBwRYgu33O6 FuaeCdE21exu7UFpLy9ivLS89YO83mWR0ul7vRFyKqU8OnFoAAKIT3KRhGvh/t3FJypL+ljykzJ n7+ExJEl7dxuqGKhdjUhpC+PVMWDuOvQTdNaKfXDXz8YcgEDBcIC+142VW5975qZcXpS1pXYofB eBHlLHYoIFSsrzKmrPdmsLx4Ce6Cv9Uoiv3acActcQqmXKYFxUWjl3y+GifR2PsYHmuI5pKdvme CF5mNxNvMUee1uLnmFNGYGq2x3Nskblp8sBOIPEgIoiKVfoywtlMNnkSQhPamaQG7DmKk3krI86 HCY3SqLywXkOi/ORxZw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-07_04,2026-09-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1011 impostorscore=0 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609070180 On 8/28/2026 12:56 AM, Mukesh Savaliya wrote: > > > On 8/24/2026 4:55 PM, Jyothi Kumar Seerapu wrote: >> Add I2C High-Speed (HS) mode support for the Qualcomm GENI I2C >> controller, detecting HS mode requests based on a 3.4 MHz bus >> frequency. > > what's the detecting here ? HS mode itself is 3.4 MHz freq. > may be you be you can start with current support freq modes and not > supported.> >> I2C HS mode is supported by the underlying QUP hardware starting with >> QUPv3 core version 4.3 (per the GENI/QUP Hardware Programming Guide). >> This series adds the driver support to detect that capability and > is this detect things repeating ?> enable HS-mode transfers on SoCs > whose QUP core version meets that >> requirement, rather than tying HS mode to any specific peripheral. >> >> Patch 1 (dmaengine: qcom-gpi) is for GPI DMA transfers and adds >> a CONFIG1 TRE to the GPI DMA engine to convey HS-specific timing >> parameters (tcycle_cnt/tlow_cnt) to the hardware. >> > Patch 1 is to convey config parameters for HS mode in GPI DMA tranfser. > >> Patch 2 (i2c: qcom-geni) handles FIFO/SE-DMA transfers; It configures >> the GENI controller's source clock and timing accordingly, and adds >> the HS-specific FIFO/SE-DMA opcodes and master-code preamble needed >> to switch the bus from Fast Mode Plus to HS speed. >> > > Like above just say high level in short, individual patch will add more > details in its commit log. > Okay, i will add the below commit description. The GENI I2C driver currently supports Standard (100 KHz), Fast (400 KHz), and Fast Mode Plus (1 MHz) speeds, but not High-Speed (HS) mode (3.4 MHz). The underlying QUP hardware supports I2C HS mode starting with QUPv3 core version 4.3, per the GENI/QUP Hardware Programming Guide. Add driver support to enable HS-mode transfers based on that QUP core version. Patch 1 (dmaengine: qcom-gpi) adds a CONFIG1 TRE to convey HS-mode timing parameters (tcycle_cnt/tlow_cnt) for GPI DMA transfers. Patch 2 (i2c: qcom-geni) adds HS-mode support for FIFO/SE-DMA transfers, including the required clock/timing configuration and master-code preamble. >> Signed-off-by: Jyothi Kumar Seerapu >> --- >> Jyothi Kumar Seerapu (2): >>        dmaengine: qcom-gpi: Add I2C High-Speed mode configuration support >>        i2c: qcom-geni: Add support for I2C High-Speed mode >> >>   drivers/dma/qcom/gpi.c             |  54 +++++++++++++-- >>   drivers/i2c/busses/i2c-qcom-geni.c | 133 +++++++++++++++++++++++++++ >> ++++++---- >>   include/linux/dma/qcom-gpi-dma.h   |  28 +++++++- >>   3 files changed, 196 insertions(+), 19 deletions(-) >> --- >> base-commit: 7079a12d7506b07fb53b54a664bfad5fa9b16d70 >> change-id: 20260821-i2c-hs-408768509865 >> >> Best regards, >> -- >> Jyothi Kumar Seerapu >> >