From: Vaishnav Achath <vaishnav.a@ti.com>
To: "Péter Ujfalusi" <peter.ujfalusi@gmail.com>,
vkoul@kernel.org, dmaengine@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: <nm@ti.com>, <vigneshr@ti.com>, <p.yadav@ti.com>,
<j-keerthy@ti.com>, <m-khayami@ti.com>, <stanley_liu@ti.com>
Subject: Re: [PATCH] dma: ti: k3-udma: Reset UDMA_CHAN_RT byte counters to prevent overflow
Date: Wed, 27 Jul 2022 20:16:39 +0530 [thread overview]
Message-ID: <df8b6249-93af-a323-3518-a1e0106b5c03@ti.com> (raw)
In-Reply-To: <ad6dcdb8-8d4d-6f8b-38de-be2756a39028@gmail.com>
Hi Peter, Vinod,
On 09/07/22 11:50, Péter Ujfalusi wrote:
>
>
> On 7/4/22 14:13, Vaishnav Achath wrote:
>> UDMA_CHAN_RT_*BCNT_REG stores the real-time channel bytecount statistics.
>> These registers are 32-bit hardware counters and the driver uses these
>> counters to monitor the operational progress status for a channel, when
>> transferring more than 4GB of data it was observed that these counters
>> overflow and completion calculation of a operation gets affected and the
>> transfer hangs indefinitely.
>>
>> This commit adds changes to decrease the byte count for every complete
>> transaction so that these registers never overflow and the proper byte
>> count statistics is maintained for ongoing transaction by the RT counters.
>>
>> Earlier uc->bcnt used to maintain a count of the completed bytes at driver
>> side, since the RT counters maintain the statistics of current transaction
>> now, the maintenance of uc->bcnt is not necessary.
>
> Thanks for the patch,
>
>> Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
>> ---
>> drivers/dma/ti/k3-udma.c | 27 +++++++++++++++++++--------
>> 1 file changed, 19 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
>> index 2f0d2c68c93c..0f91a3e47c19 100644
>> --- a/drivers/dma/ti/k3-udma.c
>> +++ b/drivers/dma/ti/k3-udma.c
>> @@ -300,8 +300,6 @@ struct udma_chan {
>>
>> struct udma_tx_drain tx_drain;
>>
>> - u32 bcnt; /* number of bytes completed since the start of the channel */
>> -
>> /* Channel configuration parameters */
>> struct udma_chan_config config;
>>
>> @@ -757,6 +755,22 @@ static void udma_reset_rings(struct udma_chan *uc)
>> }
>> }
>>
>> +static void udma_decrement_byte_counters(struct udma_chan *uc, u32 val)
>> +{
>> + if (uc->tchan) {
>> + udma_tchanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val);
>> + udma_tchanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val);
>> + if (!uc->bchan)
>> + udma_tchanrt_write(uc, UDMA_CHAN_RT_PEER_BCNT_REG, val);
>> + }
>> +
>> + if (uc->rchan) {
>> + udma_rchanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val);
>> + udma_rchanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val);
>> + udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_BCNT_REG, val);
>> + }
>
> In case of MEM_TO_MEM (or the not implemented DEV_TO_DEV) we use the
> tchan's counter for position tracking, but we have the pair anyways (UDMA).
> if ((uc->desc->dir == DMA_DEV_TO_MEM)
> rchan bcnt reset
> else
> tchan bcnt reset
>
>> +}
>> +
>> static void udma_reset_counters(struct udma_chan *uc)
>> {
>> u32 val;
>> @@ -790,8 +804,6 @@ static void udma_reset_counters(struct udma_chan *uc)
>> val = udma_rchanrt_read(uc, UDMA_CHAN_RT_PEER_BCNT_REG);
>> udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_BCNT_REG, val);
>> }
>> -
>> - uc->bcnt = 0;
>> }
>>
>> static int udma_reset_chan(struct udma_chan *uc, bool hard)
>> @@ -1115,8 +1127,8 @@ static void udma_check_tx_completion(struct work_struct *work)
>> if (uc->desc) {
>> struct udma_desc *d = uc->desc;
>>
>> - uc->bcnt += d->residue;
>> udma_start(uc);
>> + udma_decrement_byte_counters(uc, d->residue);
>
> Why not before udma_start()?
Thank you for your review and feedback, I have updated the addressed items in
V2, Sorry for the delay in responding.
V2: https://patchwork.kernel.org/project/linux-dmaengine/patch/20220727140837.25877-1-vaishnav.a@ti.com/
>
>> vchan_cookie_complete(&d->vd);
>> break;
>> }
>> @@ -1168,8 +1180,8 @@ static irqreturn_t udma_ring_irq_handler(int irq, void *data)
>> vchan_cyclic_callback(&d->vd);
>> } else {
>> if (udma_is_desc_really_done(uc, d)) {
>> - uc->bcnt += d->residue;
>> udma_start(uc);
>> + udma_decrement_byte_counters(uc, d->residue);
>> vchan_cookie_complete(&d->vd);
>> } else {
>> schedule_delayed_work(&uc->tx_drain.work,
>> @@ -1204,7 +1216,7 @@ static irqreturn_t udma_udma_irq_handler(int irq, void *data)
>> vchan_cyclic_callback(&d->vd);
>> } else {
>> /* TODO: figure out the real amount of data */
>> - uc->bcnt += d->residue;
>> + udma_decrement_byte_counters(uc, d->residue);
>> udma_start(uc);
>> vchan_cookie_complete(&d->vd);
>> }
>> @@ -3809,7 +3821,6 @@ static enum dma_status udma_tx_status(struct dma_chan *chan,
>> bcnt = udma_tchanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
>> }
>>
>> - bcnt -= uc->bcnt;
>> if (bcnt && !(bcnt % uc->desc->residue))
>> residue = 0;
>> else
>
--
Thanks and Regards,
Vaishnav
next prev parent reply other threads:[~2022-07-27 14:47 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-04 11:13 [PATCH] dma: ti: k3-udma: Reset UDMA_CHAN_RT byte counters to prevent overflow Vaishnav Achath
2022-07-09 6:20 ` Péter Ujfalusi
2022-07-27 14:46 ` Vaishnav Achath [this message]
2022-07-21 13:32 ` Vinod Koul
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