From: Jon Hunter <jonathanh@nvidia.com>
To: Akhil R <akhilrajeev@nvidia.com>
Cc: <dan.j.williams@intel.com>, <dmaengine@vger.kernel.org>,
<kyarlagadda@nvidia.com>, <ldewangan@nvidia.com>,
<linux-kernel@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<p.zabel@pengutronix.de>, <rgumasta@nvidia.com>,
<thierry.reding@gmail.com>, <vkoul@kernel.org>,
Pavan Kunapuli <pkunapuli@nvidia.com>
Subject: Re: [PATCH v7 2/4] dmaengine: tegra: Add tegra gpcdma driver
Date: Fri, 24 Sep 2021 00:27:22 +0100 [thread overview]
Message-ID: <f166f8f2-8106-c229-8b2d-f97c484dbdde@nvidia.com> (raw)
In-Reply-To: <1632383484-23487-3-git-send-email-akhilrajeev@nvidia.com>
On 23/09/2021 08:51, Akhil R wrote:
> Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver
> supports dma transfers between memory to memory, IO peripheral to memory
> and memory to IO peripheral.
>
> Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
> Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> ---
> drivers/dma/Kconfig | 12 +
> drivers/dma/Makefile | 1 +
> drivers/dma/tegra186-gpc-dma.c | 1354 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1367 insertions(+)
> create mode 100644 drivers/dma/tegra186-gpc-dma.c
...
> +static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
> + dma_cookie_t cookie,
> + struct dma_tx_state *txstate)
> +{
> + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
> + struct tegra_dma_desc *dma_desc = NULL;
> + struct virt_dma_desc *vd;
> + unsigned int residual;
> + enum dma_status ret;
> + unsigned long flags;
> +
> + raw_spin_lock_irqsave(&tdc->lock, flags);
> +
> + ret = dma_cookie_status(dc, cookie, txstate);
> + if (ret == DMA_COMPLETE) {
> + raw_spin_unlock_irqrestore(&tdc->lock, flags);
> + return ret;
> + }
> +
> + vd = vchan_find_desc(&tdc->vc, cookie);
> + if (vd)
> + dma_desc = vd_to_tegra_dma_desc(vd);
This first case implies that the transfer has not started yet and so the
residual is just dma_desc->bytes_requested.
> + else if (tdc->dma_desc && tdc->dma_desc->vd.tx.cookie == cookie)
> + dma_desc = tdc->dma_desc;
> +
> + if (dma_desc) {
> + residual = dma_desc->bytes_requested -
> + (dma_desc->bytes_transferred %
> + dma_desc->bytes_requested);
> + dma_set_residue(txstate, residual);
> + } else {
> + dev_err(tdc2dev(tdc), "cookie %d is not found\n", cookie);
> + }
> +
> + raw_spin_unlock_irqrestore(&tdc->lock, flags);
> + return ret;
> +}
> +
> +static inline int get_bus_width(struct tegra_dma_channel *tdc,
> + enum dma_slave_buswidth slave_bw)
> +{
> + switch (slave_bw) {
> + case DMA_SLAVE_BUSWIDTH_1_BYTE:
> + return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8;
> + case DMA_SLAVE_BUSWIDTH_2_BYTES:
> + return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16;
> + case DMA_SLAVE_BUSWIDTH_4_BYTES:
> + return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32;
> + default:
> + dev_err(tdc2dev(tdc), "given slave bus width is not supported\n");
> + return -EINVAL;
> + }
> +}
> +
> +static inline int get_burst_size_by_len(int len)
> +{
> + int ret;
> +
> + /* Get burst size based on the first set bit */
> + switch (ffs(len)) {
> + case 0:
> + case 1:
> + case 2:
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_1;
> + break;
> + case 3:
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_2;
> + break;
> + case 4:
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_4;
> + break;
> + case 5:
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_8;
> + break;
> + default:
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_16;
> + break;
> + }
> +
> + return ret;
> +}
> +
> +static inline int get_burst_size(struct tegra_dma_channel *tdc,
> + u32 burst_size,
> + enum dma_slave_buswidth slave_bw,
> + int len)
> +{
> + int burst_mmio_width, burst_byte, ret;
> +
> + /*
> + * burst_size from client is in terms of the bus_width.
> + * convert that into words.
> + */
> + burst_byte = burst_size * slave_bw;
> + burst_mmio_width = ffs(burst_byte / 4);
> +
> + /* Get burst size based on the first set bit */
> + switch (burst_mmio_width) {
> + case 0:
> + ret = get_burst_size_by_len(len);
> + break;
> + case 1:
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_1;
> + break;
> + case 2:
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_2;
> + break;
> + case 3:
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_4;
> + break;
> + case 4:
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_8;
> + break;
> + default:
> + ret = TEGRA_GPCDMA_MMIOSEQ_BURST_16;
> + break;
> + }
> +
> + return ret;
> +}
Something seems a bit odd here in the sense that if burst_mmio_width ==
0, we could still end up with a burst of 16? I am not sure I understand
this logic.
Jon
--
nvpublic
next prev parent reply other threads:[~2021-09-23 23:27 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-17 14:11 [PATCH v6 0/4] Add Nvidia Tegra GPC-DMA driver Akhil R
2021-09-17 14:11 ` [PATCH v6 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma Akhil R
2021-09-17 14:11 ` [PATCH v6 2/4] dmaengine: tegra: Add tegra gpcdma driver Akhil R
2021-09-17 15:36 ` Jon Hunter
2021-09-22 14:46 ` Akhil R
2021-09-23 12:22 ` Jon Hunter
2021-09-23 12:51 ` Akhil R
2021-09-23 13:20 ` Jon Hunter
2021-09-17 14:11 ` [PATCH v6 3/4] arm64: defconfig: tegra: Enable GPCDMA Akhil R
2021-09-17 14:11 ` [PATCH v6 4/4] arm64: tegra: Add GPCDMA node for tegra186 and tegra194 Akhil R
2021-09-23 7:51 ` [PATCH v7 0/4] Add Nvidia Tegra GPC-DMA driver Akhil R
2021-09-23 7:51 ` [PATCH v7 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma Akhil R
2021-09-23 22:35 ` Jon Hunter
2021-09-23 7:51 ` [PATCH v7 2/4] dmaengine: tegra: Add tegra gpcdma driver Akhil R
2021-09-23 23:27 ` Jon Hunter [this message]
2021-09-23 7:51 ` [PATCH v7 3/4] arm64: defconfig: tegra: Enable GPCDMA Akhil R
2021-09-23 7:51 ` [PATCH v7 4/4] arm64: tegra: Add GPCDMA node for tegra186 and tegra194 Akhil R
2021-09-23 23:20 ` Jon Hunter
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