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Tue, 22 Apr 2025 02:35:26 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: T8f64d9338f7a15a8 Date: Tue, 22 Apr 2025 08:34:55 +0200 From: "Arnd Bergmann" To: "Ben Collins" , dmaengine@vger.kernel.org Cc: "Zhang Wei" , "Vinod Koul" , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Message-Id: In-Reply-To: <2025042122-bizarre-ibex-b7ed42@boujee-and-buff> References: <2025042122-bizarre-ibex-b7ed42@boujee-and-buff> Subject: Re: [PATCH] fsldma: Support 40 bit DMA addresses where capable Content-Type: text/plain Content-Transfer-Encoding: 7bit On Tue, Apr 22, 2025, at 04:49, Ben Collins wrote: > On 64-bit QorIQ platforms like T4240, the CPU supports 40-bit addressing > and memory configurations > 64GiB. The fsldma driver is limiting itself > to only 64GiB in all Elo configurations. > > Setup fsldma driver to make use of the full 40-bit addressing space, > specifically on the e5500 and e6500 CPUs. I don't think making the mask depend on a compile-time option is correct, e.g. when you build a combined 32-bit kernel for e500 and e5500, you set a different mask compared to an e500-only kernel. The question here is whether the mask is a limitation of the IP block or the bus it's connected to, of if there is any limitation at all: - The driver just writes the DMA address as a 64-bit register, so most likely the DMA device can in fact do wider addressing, and any limitation is either in the bus or the available memory - SoCs that don't set a dma-ranges property in the parent bus are normally still capped to 32 bit DMA. I don't see those properties, so unless there is a special hack on those chips, you get 32 bit DMA regardless of what DMA mask the driver requests - If there are chips that have more than 64GB of RAM installed but have a limitation in the way the DMA engine is wired up to 36 bits, that should be reflected in the dma-ranges property, not the device driver. - If the limitation is indeed specific to the version of the IP block, this would normally need to be detected based on the compatible string of the DMA engine itself, not a compile time setting. Arnd