* Re: [PATCHv2] dmaengine: st_fdma: simplify allocation
From: Rosen Penev @ 2026-06-08 20:52 UTC (permalink / raw)
To: Frank Li
Cc: dmaengine, Patrice Chotard, Vinod Koul, Frank Li, Kees Cook,
Gustavo A. R. Silva, moderated list:ARM/STI ARCHITECTURE,
open list,
open list:KERNEL HARDENING (not covered by other areas):Keyword:b__counted_by(_le|_be|_ptr)?b
In-Reply-To: <aibs9gb5M4-gbCFY@SMW015318>
On Mon, Jun 8, 2026 at 9:25 AM Frank Li <Frank.li@oss.nxp.com> wrote:
>
> On Sun, Jun 07, 2026 at 10:18:29PM -0700, Rosen Penev wrote:
>
> Nit: dmaengine: st_fdma: simplify allocation by using flexible array
that's in the description. Did it that was to not have it as long,
flexible array member is the proper terminology.
>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
>
> > Use a flexible array member to combine kzalloc and kcalloc to a single
> > allocation.
> >
> > Add __counted_by for extra runtime analysis. Assign counting variable
> > after allocation before any array accesses.
> >
> > Signed-off-by: Rosen Penev <rosenp@gmail.com>
> > ---
> >
^ permalink raw reply
* Re: [PATCH 4/5] dt-bindings: dma: qcom,bam-dma: Increase iommus maxItems to seven
From: Krzysztof Kozlowski @ 2026-06-08 19:49 UTC (permalink / raw)
To: Kuldeep Singh
Cc: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Vinod Koul, Thara Gopinath,
Konrad Dybcio, Frank Li, Andy Gross, Harshal Dev, linux-arm-msm,
linux-crypto, devicetree, linux-kernel, dmaengine
In-Reply-To: <289a5bca-5491-4fc2-92d9-1102aa664021@oss.qualcomm.com>
On 06/06/2026 22:59, Kuldeep Singh wrote:
> On 30-05-2026 16:09, Krzysztof Kozlowski wrote:
>> On Thu, May 21, 2026 at 06:47:11PM +0530, Kuldeep Singh wrote:
>>> Shikra bam dma engine support 7 iommu entries and not 6.
>>> Increase maxItems property for iommus to pass dtbs_check errors.
>>
>> What errors? There is no Shikra in upstream so how could we have errors?
> dt-bindings updates are prerequisites for the DT changes of ice,rng, qce
> and hence updated bindings in patch [1-4]/5.
> Also, the commit message mention about shikra and DT change is also in
> same series.
>
> I hope this clarifies.
No, nothing is clarified. This commit msg is just misleading.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 4/5] dt-bindings: dma: qcom,bam-dma: Increase iommus maxItems to seven
From: Kuldeep Singh @ 2026-06-08 18:43 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Herbert Xu, David S. Miller, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Vinod Koul, Thara Gopinath,
Konrad Dybcio, Frank Li, Andy Gross, Harshal Dev, linux-arm-msm,
linux-crypto, devicetree, linux-kernel, dmaengine
In-Reply-To: <f9a88104-9292-4cef-af48-58a722194b4a@kernel.org>
On 07-06-2026 13:43, Krzysztof Kozlowski wrote:
> On 06/06/2026 22:59, Kuldeep Singh wrote:
>> On 30-05-2026 16:09, Krzysztof Kozlowski wrote:
>>> On Thu, May 21, 2026 at 06:47:11PM +0530, Kuldeep Singh wrote:
>>>> Shikra bam dma engine support 7 iommu entries and not 6.
>>>> Increase maxItems property for iommus to pass dtbs_check errors.
>>>
>>> What errors? There is no Shikra in upstream so how could we have errors?
>> dt-bindings updates are prerequisites for the DT changes of ice,rng, qce
>> and hence updated bindings in patch [1-4]/5.
>> Also, the commit message mention about shikra and DT change is also in
>> same series.
>>
>> I hope this clarifies.
>
> No. Please explain what errors we see now.
I need to improve my commit message a bit.
Since, shikra defines 7 iommus entry and bindings say 6, observe below
error.
dma-controller@1b04000 (qcom,bam-v1.7.4): iommus: [[31, 132, 17], [31,
134, 17], [31, 146, 0], [31, 148, 17], [31, 150, 17], [31, 152, 1], [31,
159, 0]] is too long
from schema $id: http://devicetree.org/schemas/dma/qcom,bam-dma.yaml
I am attempting to update bindings firstly by increasing iommus maxItems
as a preparatory step so as to introduce qualcomm crypto DT cleanly
later with no errors.
--
Regards
Kuldeep
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: dmaengine: Add SpacemiT K1 PDMA request numbers
From: Conor Dooley @ 2026-06-08 17:33 UTC (permalink / raw)
To: Guodong Xu
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, linux-kernel, dmaengine, devicetree, linux-riscv,
spacemit
In-Reply-To: <20260607-b4-k1-pdma-req-macros-v1-1-5b2a3955007c@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 3681 bytes --]
On Sun, Jun 07, 2026 at 01:41:30PM -0400, Guodong Xu wrote:
> Add a dt-bindings header that gives symbolic names to the SpacemiT K1
> PDMA request lines of the non-secure peripherals. Device trees can use
> these K1_PDMA_* macros instead of magic numbers.
>
> Point the spacemit,k1-pdma binding's #dma-cells description at the new
> header.
>
> Signed-off-by: Guodong Xu <docular.xu@gmail.com>
> ---
> .../devicetree/bindings/dma/spacemit,k1-pdma.yaml | 4 +-
> include/dt-bindings/dma/spacemit,k1-pdma.h | 56 ++++++++++++++++++++++
> 2 files changed, 59 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml
> index ec06235baf5ca..0d4ac9849e27b 100644
> --- a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml
> +++ b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml
> @@ -35,7 +35,9 @@ properties:
> '#dma-cells':
> const: 1
> description:
> - The DMA request number for the peripheral device.
> + The single cell is the DMA request number for the peripheral device.
> + See <dt-bindings/dma/spacemit,k1-pdma.h> for the list of valid request
> + numbers.
>
> required:
> - compatible
> diff --git a/include/dt-bindings/dma/spacemit,k1-pdma.h b/include/dt-bindings/dma/spacemit,k1-pdma.h
Why does this need to be in a binding when there is no use of this in
the driver? May as well be a header, particularly if these are numbers
with a set meaning that are lifted from the TRM, rather than made up
numbers to make a driver work. The former seems likely, given you're
indexing from 3 not 0.
> new file mode 100644
> index 0000000000000..491976516550a
> --- /dev/null
> +++ b/include/dt-bindings/dma/spacemit,k1-pdma.h
> @@ -0,0 +1,56 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * This header provides DMA request number for non-secure peripherals of
> + * SpacemiT K1 PDMA.
> + *
> + * Copyright (c) 2026 Guodong Xu <docular.xu@gmail.com>
> + */
> +
> +#ifndef _DT_BINDINGS_DMA_SPACEMIT_K1_PDMA_H_
> +#define _DT_BINDINGS_DMA_SPACEMIT_K1_PDMA_H_
> +
> +#define K1_PDMA_UART0_TX 3
> +#define K1_PDMA_UART0_RX 4
> +#define K1_PDMA_UART2_TX 5
> +#define K1_PDMA_UART2_RX 6
> +#define K1_PDMA_UART3_TX 7
> +#define K1_PDMA_UART3_RX 8
> +#define K1_PDMA_UART4_TX 9
> +#define K1_PDMA_UART4_RX 10
> +#define K1_PDMA_I2C0_TX 11
> +#define K1_PDMA_I2C0_RX 12
> +#define K1_PDMA_I2C1_TX 13
> +#define K1_PDMA_I2C1_RX 14
> +#define K1_PDMA_I2C2_TX 15
> +#define K1_PDMA_I2C2_RX 16
> +#define K1_PDMA_I2C4_TX 17
> +#define K1_PDMA_I2C4_RX 18
> +#define K1_PDMA_SPI3_TX 19
> +#define K1_PDMA_SPI3_RX 20
> +#define K1_PDMA_I2S0_TX 21
> +#define K1_PDMA_I2S0_RX 22
> +#define K1_PDMA_I2S1_TX 23
> +#define K1_PDMA_I2S1_RX 24
> +#define K1_PDMA_UART5_TX 25
> +#define K1_PDMA_UART5_RX 26
> +#define K1_PDMA_UART6_TX 27
> +#define K1_PDMA_UART6_RX 28
> +#define K1_PDMA_UART7_TX 29
> +#define K1_PDMA_UART7_RX 30
> +#define K1_PDMA_UART8_TX 31
> +#define K1_PDMA_UART8_RX 32
> +#define K1_PDMA_UART9_TX 33
> +#define K1_PDMA_UART9_RX 34
> +#define K1_PDMA_I2C5_TX 35
> +#define K1_PDMA_I2C5_RX 36
> +#define K1_PDMA_I2C6_TX 37
> +#define K1_PDMA_I2C6_RX 38
> +#define K1_PDMA_I2C7_TX 39
> +#define K1_PDMA_I2C7_RX 40
> +#define K1_PDMA_I2C8_TX 41
> +#define K1_PDMA_I2C8_RX 42
> +#define K1_PDMA_CAN0_RX 43
> +#define K1_PDMA_QSPI_RX 44
> +#define K1_PDMA_QSPI_TX 45
> +
> +#endif /* _DT_BINDINGS_DMA_SPACEMIT_K1_PDMA_H_ */
>
> --
> 2.43.0
>
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^ permalink raw reply
* Re: [PATCH] dmaengine: qcom: hidma: use sysfs_emit() in sysfs show callbacks
From: Frank Li @ 2026-06-08 16:27 UTC (permalink / raw)
To: Hungyu Lin
Cc: okaya, vkoul, Frank.Li, linux-arm-kernel, linux-arm-msm,
dmaengine, linux-kernel
In-Reply-To: <20260607163119.78717-1-dennylin0707@gmail.com>
On Sun, Jun 07, 2026 at 04:31:19PM +0000, Hungyu Lin wrote:
> [You don't often get email from dennylin0707@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> Replace sprintf() and strlen() patterns in sysfs show callbacks
> with sysfs_emit().
>
> sysfs_emit() is the preferred helper for formatting sysfs output
> and simplifies the implementation.
>
> Signed-off-by: Hungyu Lin <dennylin0707@gmail.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> drivers/dma/qcom/hidma.c | 6 ++----
> drivers/dma/qcom/hidma_mgmt_sys.c | 19 ++++++++-----------
> 2 files changed, 10 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/dma/qcom/hidma.c b/drivers/dma/qcom/hidma.c
> index 5a8dca8db5ce..7a7f302a9699 100644
> --- a/drivers/dma/qcom/hidma.c
> +++ b/drivers/dma/qcom/hidma.c
> @@ -624,12 +624,10 @@ static ssize_t hidma_show_values(struct device *dev,
> {
> struct hidma_dev *mdev = dev_get_drvdata(dev);
>
> - buf[0] = 0;
> -
> if (strcmp(attr->attr.name, "chid") == 0)
> - sprintf(buf, "%d\n", mdev->chidx);
> + return sysfs_emit(buf, "%d\n", mdev->chidx);
>
> - return strlen(buf);
> + return 0;
> }
>
> static inline void hidma_sysfs_uninit(struct hidma_dev *dev)
> diff --git a/drivers/dma/qcom/hidma_mgmt_sys.c b/drivers/dma/qcom/hidma_mgmt_sys.c
> index 930eae0a6257..9672ef9ee8fc 100644
> --- a/drivers/dma/qcom/hidma_mgmt_sys.c
> +++ b/drivers/dma/qcom/hidma_mgmt_sys.c
> @@ -102,15 +102,12 @@ static ssize_t show_values(struct device *dev, struct device_attribute *attr,
> struct hidma_mgmt_dev *mdev = dev_get_drvdata(dev);
> unsigned int i;
>
> - buf[0] = 0;
> -
> for (i = 0; i < ARRAY_SIZE(hidma_mgmt_files); i++) {
> - if (strcmp(attr->attr.name, hidma_mgmt_files[i].name) == 0) {
> - sprintf(buf, "%d\n", hidma_mgmt_files[i].get(mdev));
> - break;
> - }
> + if (strcmp(attr->attr.name, hidma_mgmt_files[i].name) == 0)
> + return sysfs_emit(buf, "%d\n",
> + hidma_mgmt_files[i].get(mdev));
> }
> - return strlen(buf);
> + return 0;
> }
>
> static ssize_t set_values(struct device *dev, struct device_attribute *attr,
> @@ -143,15 +140,15 @@ static ssize_t show_values_channel(struct kobject *kobj,
> struct hidma_chan_attr *chattr;
> struct hidma_mgmt_dev *mdev;
>
> - buf[0] = 0;
> chattr = container_of(attr, struct hidma_chan_attr, attr);
> mdev = chattr->mdev;
> +
> if (strcmp(attr->attr.name, "priority") == 0)
> - sprintf(buf, "%d\n", mdev->priority[chattr->index]);
> + return sysfs_emit(buf, "%d\n", mdev->priority[chattr->index]);
> else if (strcmp(attr->attr.name, "weight") == 0)
> - sprintf(buf, "%d\n", mdev->weight[chattr->index]);
> + return sysfs_emit(buf, "%d\n", mdev->weight[chattr->index]);
>
> - return strlen(buf);
> + return 0;
> }
>
> static ssize_t set_values_channel(struct kobject *kobj,
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCHv2] dmaengine: st_fdma: simplify allocation
From: Frank Li @ 2026-06-08 16:25 UTC (permalink / raw)
To: Rosen Penev
Cc: dmaengine, Patrice Chotard, Vinod Koul, Frank Li, Kees Cook,
Gustavo A. R. Silva, moderated list:ARM/STI ARCHITECTURE,
open list,
open list:KERNEL HARDENING (not covered by other areas):Keyword:b__counted_by(_le|_be|_ptr)?b
In-Reply-To: <20260608051829.7390-1-rosenp@gmail.com>
On Sun, Jun 07, 2026 at 10:18:29PM -0700, Rosen Penev wrote:
Nit: dmaengine: st_fdma: simplify allocation by using flexible array
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Use a flexible array member to combine kzalloc and kcalloc to a single
> allocation.
>
> Add __counted_by for extra runtime analysis. Assign counting variable
> after allocation before any array accesses.
>
> Signed-off-by: Rosen Penev <rosenp@gmail.com>
> ---
>
^ permalink raw reply
* Re: [PATCH] dma: fsl_raid: replace in_be32/out_be32 with ioread32be/iowrite32be
From: Frank Li @ 2026-06-08 16:21 UTC (permalink / raw)
To: Rosen Penev; +Cc: dmaengine, Vinod Koul, Frank Li, open list
In-Reply-To: <20260608053441.12238-1-rosenp@gmail.com>
On Sun, Jun 07, 2026 at 10:34:41PM -0700, Rosen Penev wrote:
As previous said, subject should be dmaengine: fsl_raid...
> Mechanical conversion of the ppc4xx-specific accessors to the generic
> portable helpers.
what's beneafit by such replacement? Do you remove in_be32() and out_b32()
macro?
Frank
>
> As a result, enable COMPILE_TEST for extra compile coverage.
>
> Assisted-by: opencode:big-pickle
> Signed-off-by: Rosen Penev <rosenp@gmail.com>
> ---
> drivers/dma/Kconfig | 4 ++--
> drivers/dma/fsl_raid.c | 50 ++++++++++++++++++------------------------
> 2 files changed, 23 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index f16bd4059d84..302021540d76 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -242,7 +242,7 @@ config FSL_QDMA
>
> config FSL_RAID
> tristate "Freescale RAID engine Support"
> - depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
> + depends on (FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH) || COMPILE_TEST
> select DMA_ENGINE
> select DMA_ENGINE_RAID
> help
> @@ -448,7 +448,7 @@ config MOXART_DMA
> select DMA_VIRTUAL_CHANNELS
> help
> Enable support for the MOXA ART SoC DMA controller.
> -
> +
> Say Y here if you enabled MMP ADMA, otherwise say N.
>
> config MPC512X_DMA
> diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c
> index 99945845d8b5..dedd4a83ac72 100644
> --- a/drivers/dma/fsl_raid.c
> +++ b/drivers/dma/fsl_raid.c
> @@ -114,7 +114,7 @@ static void fsl_re_issue_pending(struct dma_chan *chan)
>
> spin_lock_irqsave(&re_chan->desc_lock, flags);
> avail = FSL_RE_SLOT_AVAIL(
> - in_be32(&re_chan->jrregs->inbring_slot_avail));
> + ioread32be(&re_chan->jrregs->inbring_slot_avail));
>
> list_for_each_entry_safe(desc, _desc, &re_chan->submit_q, node) {
> if (!avail)
> @@ -127,7 +127,7 @@ static void fsl_re_issue_pending(struct dma_chan *chan)
>
> re_chan->inb_count = (re_chan->inb_count + 1) &
> FSL_RE_RING_SIZE_MASK;
> - out_be32(&re_chan->jrregs->inbring_add_job, FSL_RE_ADD_JOB(1));
> + iowrite32be(FSL_RE_ADD_JOB(1), &re_chan->jrregs->inbring_add_job);
> avail--;
> }
> spin_unlock_irqrestore(&re_chan->desc_lock, flags);
> @@ -167,7 +167,7 @@ static void fsl_re_dequeue(struct tasklet_struct *t)
> fsl_re_cleanup_descs(re_chan);
>
> spin_lock_irqsave(&re_chan->desc_lock, flags);
> - count = FSL_RE_SLOT_FULL(in_be32(&re_chan->jrregs->oubring_slot_full));
> + count = FSL_RE_SLOT_FULL(ioread32be(&re_chan->jrregs->oubring_slot_full));
> while (count--) {
> found = 0;
> hwdesc = &re_chan->oub_ring_virt_addr[re_chan->oub_count];
> @@ -192,8 +192,7 @@ static void fsl_re_dequeue(struct tasklet_struct *t)
> oub_count = (re_chan->oub_count + 1) & FSL_RE_RING_SIZE_MASK;
> re_chan->oub_count = oub_count;
>
> - out_be32(&re_chan->jrregs->oubring_job_rmvd,
> - FSL_RE_RMVD_JOB(1));
> + iowrite32be(FSL_RE_RMVD_JOB(1), &re_chan->jrregs->oubring_job_rmvd);
> }
> spin_unlock_irqrestore(&re_chan->desc_lock, flags);
> }
> @@ -206,7 +205,7 @@ static irqreturn_t fsl_re_isr(int irq, void *data)
>
> re_chan = dev_get_drvdata((struct device *)data);
>
> - irqstate = in_be32(&re_chan->jrregs->jr_interrupt_status);
> + irqstate = ioread32be(&re_chan->jrregs->jr_interrupt_status);
> if (!irqstate)
> return IRQ_NONE;
>
> @@ -216,13 +215,13 @@ static irqreturn_t fsl_re_isr(int irq, void *data)
> * need to do something more than just crashing
> */
> if (irqstate & FSL_RE_ERROR) {
> - status = in_be32(&re_chan->jrregs->jr_status);
> + status = ioread32be(&re_chan->jrregs->jr_status);
> dev_err(re_chan->dev, "chan error irqstate: %x, status: %x\n",
> irqstate, status);
> }
>
> /* Clear interrupt */
> - out_be32(&re_chan->jrregs->jr_interrupt_status, FSL_RE_CLR_INTR);
> + iowrite32be(FSL_RE_CLR_INTR, &re_chan->jrregs->jr_interrupt_status);
>
> tasklet_schedule(&re_chan->irqtask);
>
> @@ -708,30 +707,23 @@ static int fsl_re_chan_probe(struct platform_device *ofdev,
> }
>
> /* Program the Inbound/Outbound ring base addresses and size */
> - out_be32(&chan->jrregs->inbring_base_h,
> - chan->inb_phys_addr & FSL_RE_ADDR_BIT_MASK);
> - out_be32(&chan->jrregs->oubring_base_h,
> - chan->oub_phys_addr & FSL_RE_ADDR_BIT_MASK);
> - out_be32(&chan->jrregs->inbring_base_l,
> - chan->inb_phys_addr >> FSL_RE_ADDR_BIT_SHIFT);
> - out_be32(&chan->jrregs->oubring_base_l,
> - chan->oub_phys_addr >> FSL_RE_ADDR_BIT_SHIFT);
> - out_be32(&chan->jrregs->inbring_size,
> - FSL_RE_RING_SIZE << FSL_RE_RING_SIZE_SHIFT);
> - out_be32(&chan->jrregs->oubring_size,
> - FSL_RE_RING_SIZE << FSL_RE_RING_SIZE_SHIFT);
> + iowrite32be(chan->inb_phys_addr & FSL_RE_ADDR_BIT_MASK, &chan->jrregs->inbring_base_h);
> + iowrite32be(chan->oub_phys_addr & FSL_RE_ADDR_BIT_MASK, &chan->jrregs->oubring_base_h);
> + iowrite32be(chan->inb_phys_addr >> FSL_RE_ADDR_BIT_SHIFT, &chan->jrregs->inbring_base_l);
> + iowrite32be(chan->oub_phys_addr >> FSL_RE_ADDR_BIT_SHIFT, &chan->jrregs->oubring_base_l);
> + iowrite32be(FSL_RE_RING_SIZE << FSL_RE_RING_SIZE_SHIFT, &chan->jrregs->inbring_size);
> + iowrite32be(FSL_RE_RING_SIZE << FSL_RE_RING_SIZE_SHIFT, &chan->jrregs->oubring_size);
>
> /* Read LIODN value from u-boot */
> - status = in_be32(&chan->jrregs->jr_config_1) & FSL_RE_REG_LIODN_MASK;
> + status = ioread32be(&chan->jrregs->jr_config_1) & FSL_RE_REG_LIODN_MASK;
>
> /* Program the CFG reg */
> - out_be32(&chan->jrregs->jr_config_1,
> - FSL_RE_CFG1_CBSI | FSL_RE_CFG1_CBS0 | status);
> + iowrite32be(FSL_RE_CFG1_CBSI | FSL_RE_CFG1_CBS0 | status, &chan->jrregs->jr_config_1);
>
> dev_set_drvdata(chandev, chan);
>
> /* Enable RE/CHAN */
> - out_be32(&chan->jrregs->jr_command, FSL_RE_ENABLE);
> + iowrite32be(FSL_RE_ENABLE, &chan->jrregs->jr_command);
>
> return 0;
>
> @@ -768,15 +760,15 @@ static int fsl_re_probe(struct platform_device *ofdev)
> return -EBUSY;
>
> /* Program the RE mode */
> - out_be32(&re_priv->re_regs->global_config, FSL_RE_NON_DPAA_MODE);
> + iowrite32be(FSL_RE_NON_DPAA_MODE, &re_priv->re_regs->global_config);
>
> /* Program Galois Field polynomial */
> - out_be32(&re_priv->re_regs->galois_field_config, FSL_RE_GFM_POLY);
> + iowrite32be(FSL_RE_GFM_POLY, &re_priv->re_regs->galois_field_config);
>
> dev_info(dev, "version %x, mode %x, gfp %x\n",
> - in_be32(&re_priv->re_regs->re_version_id),
> - in_be32(&re_priv->re_regs->global_config),
> - in_be32(&re_priv->re_regs->galois_field_config));
> + ioread32be(&re_priv->re_regs->re_version_id),
> + ioread32be(&re_priv->re_regs->global_config),
> + ioread32be(&re_priv->re_regs->galois_field_config));
>
> dma_dev = &re_priv->dma_dev;
> dma_dev->dev = dev;
> --
> 2.54.0
>
^ permalink raw reply
* [PATCH v4 10/10] arm64: dts: qcom: shikra: Enable Bluetooth and WiFi on EVK boards
From: Komal Bajaj @ 2026-06-08 13:10 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Yepuri Siddu, Miaoqing Pan
In-Reply-To: <20260608-shikra-dt-m1-v4-0-2114300594a6@oss.qualcomm.com>
Enable Bluetooth and WiFi connectivity on Shikra CQM, CQS and IQS
EVK boards using the WCN3988 combo chip.
For Bluetooth, enable uart8 and add WCN3988 Bluetooth node with
board-specific regulator supplies across CQM, CQS and IQS Shikra
EVK boards.
For WiFi, introduce the wcn3990-wifi hardware node in shikra.dtsi
with register space, interrupts, IOMMU configuration and reserved
memory. The node is kept disabled by default and enabled per-board
with the appropriate PMIC supply connections and calibration variant
selection.
Co-developed-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
Co-developed-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 59 +++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 59 +++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 15 +++++++
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 67 +++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra.dtsi | 23 ++++++++++
5 files changed, 223 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
index b112b21b1d79..683b5245923b 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
@@ -16,11 +16,48 @@ / {
aliases {
mmc0 = &sdhc_1;
serial0 = &uart0;
+ serial1 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
+
+ wcn3988-pmu {
+ compatible = "qcom,wcn3988-pmu";
+
+ pinctrl-0 = <&sw_ctrl_default>;
+ pinctrl-names = "default";
+
+ vddio-supply = <&pm4125_l7>;
+ vddxo-supply = <&pm4125_l13>;
+ vddrf-supply = <&pm4125_l10>;
+ vddch0-supply = <&pm4125_l22>;
+
+ swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ vreg_pmu_io: ldo0 {
+ regulator-name = "vreg_pmu_io";
+ };
+
+ vreg_pmu_xo: ldo1 {
+ regulator-name = "vreg_pmu_xo";
+ };
+
+ vreg_pmu_rf: ldo2 {
+ regulator-name = "vreg_pmu_rf";
+ };
+
+ vreg_pmu_ch0: ldo3 {
+ regulator-name = "vreg_pmu_ch0";
+ };
+
+ vreg_pmu_ch1: ldo4 {
+ regulator-name = "vreg_pmu_ch1";
+ };
+ };
+ };
};
&remoteproc_cdsp {
@@ -57,3 +94,25 @@ &sdhc_1 {
status = "okay";
};
+
+&uart8 {
+ status = "okay";
+
+ bluetooth {
+ vddio-supply = <&vreg_pmu_io>;
+ vddxo-supply = <&vreg_pmu_xo>;
+ vddrf-supply = <&vreg_pmu_rf>;
+ vddch0-supply = <&vreg_pmu_ch0>;
+ };
+};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&pm4125_l7>;
+ vdd-1.8-xo-supply = <&vreg_pmu_xo>;
+ vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
+ vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
+ qcom,calibration-variant = "Shikra_EVK";
+ firmware-name = "shikra";
+
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
index e62ba5aef71f..26ff8007a819 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
@@ -16,11 +16,48 @@ / {
aliases {
mmc0 = &sdhc_1;
serial0 = &uart0;
+ serial1 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
+
+ wcn3988-pmu {
+ compatible = "qcom,wcn3988-pmu";
+
+ pinctrl-0 = <&sw_ctrl_default>;
+ pinctrl-names = "default";
+
+ vddio-supply = <&pm4125_l7>;
+ vddxo-supply = <&pm4125_l13>;
+ vddrf-supply = <&pm4125_l10>;
+ vddch0-supply = <&pm4125_l22>;
+
+ swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ vreg_pmu_io: ldo0 {
+ regulator-name = "vreg_pmu_io";
+ };
+
+ vreg_pmu_xo: ldo1 {
+ regulator-name = "vreg_pmu_xo";
+ };
+
+ vreg_pmu_rf: ldo2 {
+ regulator-name = "vreg_pmu_rf";
+ };
+
+ vreg_pmu_ch0: ldo3 {
+ regulator-name = "vreg_pmu_ch0";
+ };
+
+ vreg_pmu_ch1: ldo4 {
+ regulator-name = "vreg_pmu_ch1";
+ };
+ };
+ };
};
&remoteproc_cdsp {
@@ -57,3 +94,25 @@ &sdhc_1 {
status = "okay";
};
+
+&uart8 {
+ status = "okay";
+
+ bluetooth {
+ vddio-supply = <&vreg_pmu_io>;
+ vddxo-supply = <&vreg_pmu_xo>;
+ vddrf-supply = <&vreg_pmu_rf>;
+ vddch0-supply = <&vreg_pmu_ch0>;
+ };
+};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&pm4125_l7>;
+ vdd-1.8-xo-supply = <&vreg_pmu_xo>;
+ vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
+ vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
+ qcom,calibration-variant = "Shikra_EVK";
+ firmware-name = "shikra";
+
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
index 8b03d4eafa6d..a79f44aff968 100644
--- a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
@@ -8,7 +8,22 @@ &qupv3_0 {
status = "okay";
};
+&tlmm {
+ sw_ctrl_default: sw-ctrl-default-state {
+ pins = "gpio88";
+ function = "gpio";
+ bias-pull-down;
+ };
+};
+
&uart0 {
status = "okay";
};
+&uart8 {
+ bluetooth {
+ compatible = "qcom,wcn3988-bt";
+ max-speed = <3200000>;
+ };
+};
+
diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
index 727809430fd1..fd691d53a0fa 100644
--- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
@@ -16,11 +16,56 @@ / {
aliases {
mmc0 = &sdhc_1;
serial0 = &uart0;
+ serial1 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
+
+ vreg_wcn_3p3: regulator-wcn-3p3 {
+ compatible = "regulator-fixed";
+ regulator-name = "wcn_3p3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ wcn3988-pmu {
+ compatible = "qcom,wcn3988-pmu";
+
+ pinctrl-0 = <&sw_ctrl_default>;
+ pinctrl-names = "default";
+
+ vddio-supply = <&pm8150_s4>;
+ vddxo-supply = <&pm8150_l12>;
+ vddrf-supply = <&pm8150_l8>;
+ vddch0-supply = <&vreg_wcn_3p3>;
+
+ swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ vreg_pmu_io: ldo0 {
+ regulator-name = "vreg_pmu_io";
+ };
+
+ vreg_pmu_xo: ldo1 {
+ regulator-name = "vreg_pmu_xo";
+ };
+
+ vreg_pmu_rf: ldo2 {
+ regulator-name = "vreg_pmu_rf";
+ };
+
+ vreg_pmu_ch0: ldo3 {
+ regulator-name = "vreg_pmu_ch0";
+ };
+
+ vreg_pmu_ch1: ldo4 {
+ regulator-name = "vreg_pmu_ch1";
+ };
+ };
+ };
};
&remoteproc_cdsp {
@@ -57,3 +102,25 @@ &sdhc_1 {
status = "okay";
};
+
+&uart8 {
+ status = "okay";
+
+ bluetooth {
+ vddio-supply = <&vreg_pmu_io>;
+ vddxo-supply = <&vreg_pmu_xo>;
+ vddrf-supply = <&vreg_pmu_rf>;
+ vddch0-supply = <&vreg_pmu_ch0>;
+ };
+};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&pm8150_s4>;
+ vdd-1.8-xo-supply = <&vreg_pmu_xo>;
+ vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
+ vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
+ qcom,calibration-variant = "Shikra_EVK";
+ firmware-name = "shikra";
+
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index c1f25ce89bb1..6bac6ebac8da 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -2064,6 +2064,29 @@ apps_smmu: iommu@c600000 {
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
};
+ wifi: wifi@c800000 {
+ compatible = "qcom,wcn3990-wifi";
+ reg = <0x0 0x0c800000 0x0 0x800000>;
+ reg-names = "membase";
+ memory-region = <&wlan_mem>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&apps_smmu 0x1a0 0x1>;
+ qcom,msa-fixed-perm;
+
+ status = "disabled";
+ };
+
intc: interrupt-controller@f200000 {
compatible = "arm,gic-v3";
reg = <0x0 0xf200000 0x0 0x10000>,
--
2.34.1
^ permalink raw reply related
* [PATCH v4 09/10] arm64: dts: qcom: shikra: Enable TSENS and thermal zones
From: Komal Bajaj @ 2026-06-08 13:10 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Gaurav Kohli, Dmitry Baryshkov
In-Reply-To: <20260608-shikra-dt-m1-v4-0-2114300594a6@oss.qualcomm.com>
From: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
The shikra includes one TSENS instance, with a total of 14 thermal
sensors distributed across various locations on the SoC.
The TSENS max/reset threshold is configured to 120°C in the hardware.
Enable all TSENS instances, and define the thermal zones with a hot trip
at 110°C and critical trip at 115°C.
Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 267 +++++++++++++++++++++++++++++++++++
1 file changed, 267 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 445dd8bb7269..c1f25ce89bb1 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/interconnect/qcom,shikra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -983,6 +984,18 @@ spmi_bus: spmi@1c40000 {
qcom,ee = <0>;
};
+ tsens0: thermal-sensor@4411000 {
+ compatible = "qcom,shikra-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x04411000 0x0 0x1000>,
+ <0x0 0x04410000 0x0 0x1000>;
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <14>;
+ #thermal-sensor-cells = <1>;
+ };
+
rpm_msg_ram: sram@45f0000 {
compatible = "qcom,rpm-msg-ram", "mmio-sram";
reg = <0x0 0x045f0000 0x0 0x7000>;
@@ -2180,6 +2193,260 @@ cpufreq_hw: cpufreq@fd91000 {
};
};
+ thermal_zones: thermal-zones {
+ aoss0-thermal {
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ aoss0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-0-thermal {
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu00-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-1-thermal {
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu01-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-0-thermal {
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu10-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-1-thermal {
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu11-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss0-thermal {
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpuss0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-thermal {
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpuss-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsp-thermal {
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nsp-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss0-thermal {
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ mdmss0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss1-thermal {
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ mdmss1-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera-thermal {
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ camera-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-thermal {
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ video-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-2-thermal {
+ thermal-sensors = <&tsens0 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu02-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss1-thermal {
+ thermal-sensors = <&tsens0 13>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpuss1-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
--
2.34.1
^ permalink raw reply related
* [PATCH v4 08/10] arm64: dts: qcom: shikra: Enable CDSP, LPAICP and MPSS on EVK boards
From: Komal Bajaj @ 2026-06-08 13:10 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Bibek Kumar Patro
In-Reply-To: <20260608-shikra-dt-m1-v4-0-2114300594a6@oss.qualcomm.com>
From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Enable CDSP, LPAICP and MPSS for Qualcomm's Shikra CQM, CQS and
IQS EVK board.
Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 19 +++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 19 +++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 19 +++++++++++++++++++
3 files changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
index 0a52ab9b7a4c..b112b21b1d79 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
@@ -23,6 +23,25 @@ chosen {
};
};
+&remoteproc_cdsp {
+ firmware-name = "qcom/shikra/cdsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_lpaicp {
+ firmware-name = "qcom/shikra/lpaicp.mbn",
+ "qcom/shikra/lpaicp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/shikra/cqm/qdsp6sw.mbn";
+
+ status = "okay";
+};
+
&sdhc_1 {
vmmc-supply = <&pm4125_l20>;
vqmmc-supply = <&pm4125_l14>;
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
index b3f19a64d7ae..e62ba5aef71f 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
@@ -23,6 +23,25 @@ chosen {
};
};
+&remoteproc_cdsp {
+ firmware-name = "qcom/shikra/cdsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_lpaicp {
+ firmware-name = "qcom/shikra/lpaicp.mbn",
+ "qcom/shikra/lpaicp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn";
+
+ status = "okay";
+};
+
&sdhc_1 {
vmmc-supply = <&pm4125_l20>;
vqmmc-supply = <&pm4125_l14>;
diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
index 3003a47bd759..727809430fd1 100644
--- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
@@ -23,6 +23,25 @@ chosen {
};
};
+&remoteproc_cdsp {
+ firmware-name = "qcom/shikra/cdsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_lpaicp {
+ firmware-name = "qcom/shikra/lpaicp.mbn",
+ "qcom/shikra/lpaicp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn";
+
+ status = "okay";
+};
+
&sdhc_1 {
vmmc-supply = <&pm8150_l17>;
vqmmc-supply = <&pm8150_s4>;
--
2.34.1
^ permalink raw reply related
* [PATCH v4 07/10] arm64: dts: qcom: shikra: Add CDSP, LPAICP, MPSS remoteproc PAS nodes
From: Komal Bajaj @ 2026-06-08 13:10 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Bibek Kumar Patro
In-Reply-To: <20260608-shikra-dt-m1-v4-0-2114300594a6@oss.qualcomm.com>
From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add nodes for remoteproc PAS loader for CDSP, LPAICP, MPSS subsystem.
Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 164 +++++++++++++++++++++++++++++++++++
1 file changed, 164 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 219c904fba29..445dd8bb7269 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -1798,6 +1798,170 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
};
};
+ remoteproc_mpss: remoteproc@6080000 {
+ compatible = "qcom,shikra-mpss-pas";
+ reg = <0x0 0x06080000 0x0 0x100>;
+
+ interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING 0>,
+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+
+ power-domains = <&rpmpd RPMHPD_CX>;
+
+ memory-region = <&mpss_wlan_mem>;
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING 0>;
+ mboxes = <&apcs_glb 12>;
+ qcom,remote-pid = <1>;
+ label = "mpss";
+ };
+ };
+
+ remoteproc_cdsp: remoteproc@b300000 {
+ compatible = "qcom,shikra-cdsp-pas";
+ reg = <0x0 0x0b300000 0x0 0x100000>;
+
+ interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING 0>,
+ <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+
+ power-domains = <&rpmpd RPMHPD_CX>;
+
+ memory-region = <&cdsp_mem>;
+
+ qcom,smem-states = <&cdsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING 0>;
+ mboxes = <&apcs_glb 4>;
+ qcom,remote-pid = <5>;
+ label = "cdsp";
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "cdsp";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&apps_smmu 0x0201 0x0000>;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&apps_smmu 0x0202 0x0000>;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x0203 0x0000>;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu 0x0204 0x0000>;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu 0x0205 0x0000>;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu 0x0206 0x0000>;
+ };
+
+ compute-cb@9 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <9>;
+ iommus = <&apps_smmu 0x0209 0x0000>;
+ };
+ };
+ };
+ };
+
+ remoteproc_lpaicp: remoteproc@b800000 {
+ compatible = "qcom,shikra-lpaicp-pas";
+ reg = <0x0 0x0b800000 0x0 0x200000>;
+
+ interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING 0>,
+ <&lmcu_smp2p_in 0 IRQ_TYPE_NONE>,
+ <&lmcu_smp2p_in 1 IRQ_TYPE_NONE>,
+ <&lmcu_smp2p_in 2 IRQ_TYPE_NONE>,
+ <&lmcu_smp2p_in 3 IRQ_TYPE_NONE>;
+
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ memory-region = <&lmcu_mem &lmcu_dtb_mem>;
+
+ qcom,smem-states = <&lmcu_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING 0>;
+ mboxes = <&apcs_glb 9>;
+ qcom,remote-pid = <26>;
+ label = "lpaicp";
+ };
+ };
+
sram@c11e000 {
compatible = "qcom,shikra-imem", "mmio-sram";
reg = <0x0 0x0c11e000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related
* [PATCH v4 06/10] arm64: dts: qcom: shikra: Add SMP2P nodes
From: Komal Bajaj @ 2026-06-08 13:10 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Vishnu Santhosh, Dmitry Baryshkov
In-Reply-To: <20260608-shikra-dt-m1-v4-0-2114300594a6@oss.qualcomm.com>
From: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Add SMP2P nodes for the cdsp, modem and lmcu subsystems to enable
inter-processor signalling for remoteproc state management.
Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 69 ++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 309ebe515814..219c904fba29 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -413,6 +413,75 @@ lmcu_dtb_mem: lmcu-dtb@b4702000 {
};
};
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+
+ interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING 0>;
+
+ mboxes = <&apcs_glb 6>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-lmcu {
+ compatible = "qcom,smp2p";
+ qcom,smem = <617>, <616>;
+
+ interrupts = <GIC_SPI 287 IRQ_TYPE_EDGE_RISING 0>;
+
+ mboxes = <&apcs_glb 10>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <26>;
+
+ lmcu_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ lmcu_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-mpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+
+ interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING 0>;
+
+ mboxes = <&apcs_glb 14>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
soc: soc@0 {
compatible = "simple-bus";
--
2.34.1
^ permalink raw reply related
* [PATCH v4 05/10] arm64: dts: qcom: shikra: Add cpufreq-hw, EPSS L3 interconnect and OPP tables
From: Komal Bajaj @ 2026-06-08 13:10 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Aastha Pandey, Imran Shaik, Raviteja Laggyshetty,
Sayantan Chakraborty, Konrad Dybcio, Dmitry Baryshkov
In-Reply-To: <20260608-shikra-dt-m1-v4-0-2114300594a6@oss.qualcomm.com>
Add cpufreq-hw node to support cpufreq scaling on Qualcomm Shikra SoCs.
Also, add Epoch Subsystem (EPSS) L3 interconnect provider node and OPP
tables required to scale DDR and L3 per freq-domain on Shikra SoC.
Co-developed-by: Aastha Pandey <aastha.pandey@oss.qualcomm.com>
Signed-off-by: Aastha Pandey <aastha.pandey@oss.qualcomm.com>
Co-developed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Co-developed-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Signed-off-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 125 +++++++++++++++++++++++++++++++++++
1 file changed, 125 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index ec1bfebed226..309ebe515814 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,shikra-gcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,rpm-icc.h>
#include <dt-bindings/interconnect/qcom,shikra.h>
@@ -44,6 +45,14 @@ cpu0: cpu@0 {
next-level-cache = <&l3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
};
cpu1: cpu@100 {
@@ -54,6 +63,14 @@ cpu1: cpu@100 {
next-level-cache = <&l3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
};
cpu2: cpu@200 {
@@ -64,6 +81,14 @@ cpu2: cpu@200 {
next-level-cache = <&l3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
};
cpu3: cpu@300 {
@@ -74,6 +99,14 @@ cpu3: cpu@300 {
next-level-cache = <&l2_3>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <489>;
+ clocks = <&cpufreq_hw 1>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
l2_3: l2-cache {
compatible = "cache";
@@ -132,6 +165,71 @@ memory@80000000 {
reg = <0x0 0x80000000 0x0 0x0>;
};
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-768000000 {
+ opp-hz = /bits/ 64 <768000000>;
+ opp-peak-kBps = <1200000 17817600>;
+ };
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <2188000 25804800>;
+ };
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ opp-peak-kBps = <3072000 30105600>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <4068000 38707200>;
+ };
+
+ opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ opp-peak-kBps = <6220000 43008000>;
+ };
+
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-peak-kBps = <7216000 43622400>;
+ };
+ };
+
+ cpu3_opp_table: opp-table-cpu3 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <2188000 25804800>;
+ };
+
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-peak-kBps = <3072000 30105600>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <4068000 38707200>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <6220000 43008000>;
+ };
+
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-peak-kBps = <7216000 43622400>;
+ };
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
@@ -1820,6 +1918,33 @@ frame@f42d000 {
status = "disabled";
};
};
+
+ epss_l3: interconnect@fd90000 {
+ compatible = "qcom,shikra-epss-l3";
+ reg = <0x0 0x0fd90000 0x0 0x1000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
+ cpufreq_hw: cpufreq@fd91000 {
+ compatible = "qcom,shikra-epss";
+ reg = <0x0 0x0fd91000 0x0 0x1000>,
+ <0x0 0x0fd92000 0x0 0x1000>;
+ reg-names = "freq-domain0",
+ "freq-domain1";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "dcvsh-irq-0",
+ "dcvsh-irq-1";
+
+ #freq-domain-cells = <1>;
+ #clock-cells = <1>;
+ };
};
timer {
--
2.34.1
^ permalink raw reply related
* [PATCH v4 04/10] arm64: dts: qcom: shikra: Add DDR BWMON support
From: Komal Bajaj @ 2026-06-08 13:10 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Sayantan Chakraborty, Konrad Dybcio,
Dmitry Baryshkov
In-Reply-To: <20260608-shikra-dt-m1-v4-0-2114300594a6@oss.qualcomm.com>
From: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Add CPU-to-DDR BWMON nodes and their corresponding opp tables for
Shikra SoC. This is necessary to enable power management and optimize
system performance from the perspective of dynamically changing DDR
frequencies.
Signed-off-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 40 ++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index e6ec07a865f0..ec1bfebed226 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -661,6 +661,46 @@ rclk-pins {
};
};
+ pmu@c91000 {
+ compatible = "qcom,shikra-cpu-bwmon", "qcom,sc7280-llcc-bwmon";
+ reg = <0x0 0x00c91000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <1200000>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <2188000>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <3072000>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <4068000>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <6220000>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <7216000>;
+ };
+ };
+ };
+
mem_noc: interconnect@d00000 {
compatible = "qcom,shikra-mem-noc-core";
reg = <0x0 0x00d00000 0x0 0x43080>;
--
2.34.1
^ permalink raw reply related
* [PATCH v4 03/10] arm64: dts: qcom: Add QUPv3 configuration for Shikra
From: Komal Bajaj @ 2026-06-08 13:10 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Xueyao An, Dmitry Baryshkov
In-Reply-To: <20260608-shikra-dt-m1-v4-0-2114300594a6@oss.qualcomm.com>
From: Xueyao An <xueyao.an@oss.qualcomm.com>
Add device tree support for QUPv3 serial engine protocols on Shikra.
Shikra has 10 QUP serial engines under a single QUP wrapper, all with
support of GPI DMA engines.
Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 951 +++++++++++++++++++++++++++++++++++
1 file changed, 951 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index a4334d99c1f3..e6ec07a865f0 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,shikra-gcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,rpm-icc.h>
#include <dt-bindings/interconnect/qcom,shikra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -348,6 +349,161 @@ tlmm: pinctrl@500000 {
gpio-ranges = <&tlmm 0 0 165>;
wakeup-parent = <&mpm>;
+ qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio2", "gpio3";
+ function = "qup0_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio4", "gpio5";
+ function = "qup0_se1_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio6", "gpio7";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio10", "gpio11";
+ function = "qup0_se3_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio12", "gpio13";
+ function = "qup0_se4_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio14", "gpio15";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio18", "gpio19";
+ function = "qup0_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c7_data_clk: qup-i2c7-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio20", "gpio21";
+ function = "qup0_se7_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio22", "gpio23";
+ function = "qup0_se8";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio27", "gpio26";
+ function = "qup0_se9_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio1";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio2", "gpio3", "gpio0";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_cs: qup-spi2-cs-state {
+ pins = "gpio9";
+ function = "qup0_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio6", "gpio7", "gpio8";
+ function = "qup0_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_cs: qup-spi5-cs-state {
+ pins = "gpio17";
+ function = "qup0_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio14", "gpio15", "gpio16";
+ function = "qup0_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ pins = "gpio29";
+ function = "qup0_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio18", "gpio19", "gpio28";
+ function = "qup0_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_cs: qup-spi8-cs-state {
+ pins = "gpio25";
+ function = "qup0_se8";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_data_clk: qup-spi8-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio22", "gpio23", "gpio24";
+ function = "qup0_se8";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
qup_uart0_default: qup-uart0-default-state {
pins = "gpio0", "gpio1";
function = "qup0_se0";
@@ -355,6 +511,105 @@ qup_uart0_default: qup-uart0-default-state {
bias-disable;
};
+ qup_uart1_default: qup-uart1-default-state {
+ pins = "gpio4", "gpio5";
+ function = "qup0_se1_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart2_default: qup-uart2-default-state {
+ /* TX, RX */
+ pins = "gpio8", "gpio9";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart2_cts_rts: qup-uart2-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio6", "gpio7";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart3_default: qup-uart3-default-state {
+ pins = "gpio10", "gpio11";
+ function = "qup0_se3_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart4_default: qup-uart4-default-state {
+ pins = "gpio12", "gpio13";
+ function = "qup0_se4_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart5_default: qup-uart5-default-state {
+ /* TX, RX */
+ pins = "gpio16", "gpio17";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart5_cts_rts: qup-uart5-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio14", "gpio15";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart6_default: qup-uart6-default-state {
+ /* TX, RX */
+ pins = "gpio28", "gpio29";
+ function = "qup0_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart6_cts_rts: qup-uart6-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio18", "gpio19";
+ function = "qup0_se6";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart7_default: qup-uart7-default-state {
+ pins = "gpio20", "gpio21";
+ function = "qup0_se7_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart8_default: qup-uart8-default-state {
+ /* TX, RX */
+ pins = "gpio24", "gpio25";
+ function = "qup0_se8";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart8_cts_rts: qup-uart8-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio22", "gpio23";
+ function = "qup0_se8";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart9_default: qup-uart9-default-state {
+ pins = "gpio26", "gpio27";
+ function = "qup0_se9_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
sdc1_state_on: sdc1-on-state {
clk-pins {
pins = "sdc1_clk";
@@ -604,6 +859,34 @@ opp-384000000 {
};
};
+ gpi_dma0: dma-controller@4a00000 {
+ compatible = "qcom,shikra-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x04a00000 0x0 0x60000>;
+
+ interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ dma-channels = <16>;
+ dma-channel-mask = <0xff>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0xf6 0x0>;
+ };
+
qupv3_0: geniqup@4ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x04ac0000 0x0 0x2000>;
@@ -613,10 +896,75 @@ qupv3_0: geniqup@4ac0000 {
clock-names = "m-ahb",
"s-ahb";
+ iommus = <&apps_smmu 0xe3 0x0>;
+
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ status = "disabled";
+
+ i2c0: i2c@4a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c0_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi0: spi@4a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
uart0: serial@4a80000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x04a80000 0x0 0x4000>;
@@ -638,6 +986,609 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
status = "disabled";
};
+
+ i2c1: i2c@4a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a84000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart1: serial@4a84000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a84000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart1_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c2: i2c@4a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a88000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ pinctrl-names = "default";
+
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi2: spi@4a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4a88000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@4a88000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a88000 0x0 0x4000>;
+
+ interrupts-extended = <&intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&tlmm 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart2_default>, <&qup_uart2_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c3: i2c@4a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart3: serial@4a8c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart3_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c4: i2c@4a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a90000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart4: serial@4a90000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a90000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart4_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c5: i2c@4a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi5: spi@4a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart5: serial@4a94000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart5_default>, <&qup_uart5_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c6: i2c@4a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a98000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi6: spi@4a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4a98000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart6: serial@4a98000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a98000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart6_default>, <&qup_uart6_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c7: i2c@4a9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a9c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c7_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart7: serial@4a9c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a9c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart7_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c8: i2c@4aa0000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4aa0000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 8 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 8 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c8_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi8: spi@4aa0000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4aa0000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 8 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 8 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart8: serial@4aa0000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04aa0000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart8_default>, <&qup_uart8_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c9: i2c@4aa4000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4aa4000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 9 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 9 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart9: serial@4aa4000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04aa4000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart9_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
};
sram@c11e000 {
--
2.34.1
^ permalink raw reply related
* [PATCH v4 02/10] dt-bindings: interconnect: qcom-bwmon: Add Shikra cpu-bwmon compatible
From: Komal Bajaj @ 2026-06-08 13:10 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Sayantan Chakraborty, Krzysztof Kozlowski
In-Reply-To: <20260608-shikra-dt-m1-v4-0-2114300594a6@oss.qualcomm.com>
From: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Add the Qualcomm Shikra SoC compatible string for the CPU-to-DDR
bandwidth monitor. Shikra has a BWMONv5 for CPU.
Signed-off-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
index ff64225e8281..8f6c937e44ce 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
@@ -52,6 +52,7 @@ properties:
- qcom,sa8775p-llcc-bwmon
- qcom,sc7180-llcc-bwmon
- qcom,sc8280xp-llcc-bwmon
+ - qcom,shikra-cpu-bwmon
- qcom,sm6350-cpu-bwmon
- qcom,sm8250-llcc-bwmon
- qcom,sm8550-llcc-bwmon
--
2.34.1
^ permalink raw reply related
* [PATCH v4 01/10] dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Shikra SoC
From: Komal Bajaj @ 2026-06-08 13:10 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Xueyao An, Krzysztof Kozlowski
In-Reply-To: <20260608-shikra-dt-m1-v4-0-2114300594a6@oss.qualcomm.com>
From: Xueyao An <xueyao.an@oss.qualcomm.com>
Document the GPI DMA engine on Shikra platform.
It is fully compatible with the GPI DMA engine found on SM6350,
thus using qcom,sm6350-gpi-dma as fallback compatible.
Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
index 8f9a552fe30e..54dca623223d 100644
--- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
+++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
@@ -37,6 +37,7 @@ properties:
- qcom,sc7280-gpi-dma
- qcom,sc8280xp-gpi-dma
- qcom,sdx75-gpi-dma
+ - qcom,shikra-gpi-dma
- qcom,sm6115-gpi-dma
- qcom,sm6375-gpi-dma
- qcom,sm8350-gpi-dma
--
2.34.1
^ permalink raw reply related
* [PATCH v4 00/10] arm64: dts: qcom: Extend Shikra device tree with peripheral and subsystem support
From: Komal Bajaj @ 2026-06-08 13:10 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Xueyao An, Krzysztof Kozlowski, Sayantan Chakraborty,
Dmitry Baryshkov, Konrad Dybcio, Aastha Pandey, Imran Shaik,
Raviteja Laggyshetty, Vishnu Santhosh, Bibek Kumar Patro,
Gaurav Kohli, Yepuri Siddu, Miaoqing Pan
Extend Shikra DT with peripheral and subsystem support across all SoM
variants (CQ2390M, CQ2390S, IQ2390S) and their EVK boards.
The series adds:
- QUPv3 serial engine configuration
- cpufreq-hw node for hardware-assisted CPU frequency scaling
- DDR bandwidth monitor (BWMONv5) nodes with OPP tables for dynamic
DDR frequency scaling
- EPSS L3 interconnect provider node for L3 cache frequency scaling
- CPU OPP tables to drive DDR and L3 scaling per frequency domain
- SMP2P nodes for CDSP, modem and LMCU inter-processor signalling
- Remoteproc PAS nodes for CDSP, LPAICP and MPSS subsystems
- TSENS instance with 14 thermal sensors and thermal zone definitions
- Bluetooth (WCN3988) node with board-specific regulator supplies on
all three EVK variants
- WiFi node in the SoC DTSI with board-specific power supply and
calibration variant selection on all three EVK variants
This series depends on:
- https://lore.kernel.org/all/20260527-shikra-dt-v4-0-b5ca1fa0b392@oss.qualcomm.com/
- https://lore.kernel.org/all/20260521-shikra-rproc-v3-0-2fca0bbe1ad7@oss.qualcomm.com/
- https://lore.kernel.org/linux-devicetree/20260513-tsens_binding-v1-1-1780c6a6caf2@oss.qualcomm.com/
- https://lore.kernel.org/all/20260524-shikra_epss_l3-v1-0-b1528a436134@oss.qualcomm.com/
- https://lore.kernel.org/all/20260522-shikra-cpufreq-scaling-v4-0-f042a25896c5@oss.qualcomm.com/
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
Changes in v4:
- Updated commit message for first commit of the series (Krzysztof)
- Collected tags from Dmitry and Krzysztof
- Updated wifi fimmware name (Dmitry)
- Link to v3: https://lore.kernel.org/r/20260601-shikra-dt-m1-v3-0-0fe3f8d9ec48@oss.qualcomm.com
Changes in v3:
- Add missing interrupt affinity cell (0) to GPI DMA interrupts
- Link to v2: https://lore.kernel.org/r/20260530-shikra-dt-m1-v2-0-6bb581035d13@oss.qualcomm.com
Changes in v2:
- Collected Reviewed-By tags from Dmitry and Konrad
- Squashed cpufreq_hw, EPSS and OPP tables into single commit (Dmitry)
- Removed labels from CPU OPP table entries (Dmitry)
- Squashed CQM, CQS and IQS remoteproc-enable patches into one commit (Dmitry)
- Added WCN3988 PMU support (Dmitry)
- Squashed Bluetooth and Wifi changes into one commit (Dmitry)
- Link to v1: https://lore.kernel.org/r/20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com
---
Bibek Kumar Patro (2):
arm64: dts: qcom: shikra: Add CDSP, LPAICP, MPSS remoteproc PAS nodes
arm64: dts: qcom: shikra: Enable CDSP, LPAICP and MPSS on EVK boards
Gaurav Kohli (1):
arm64: dts: qcom: shikra: Enable TSENS and thermal zones
Komal Bajaj (2):
arm64: dts: qcom: shikra: Add cpufreq-hw, EPSS L3 interconnect and OPP tables
arm64: dts: qcom: shikra: Enable Bluetooth and WiFi on EVK boards
Sayantan Chakraborty (2):
dt-bindings: interconnect: qcom-bwmon: Add Shikra cpu-bwmon compatible
arm64: dts: qcom: shikra: Add DDR BWMON support
Vishnu Santhosh (1):
arm64: dts: qcom: shikra: Add SMP2P nodes
Xueyao An (2):
dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Shikra SoC
arm64: dts: qcom: Add QUPv3 configuration for Shikra
.../devicetree/bindings/dma/qcom,gpi.yaml | 1 +
.../bindings/interconnect/qcom,msm8998-bwmon.yaml | 1 +
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 78 +
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 78 +
arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 15 +
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 86 +
arch/arm64/boot/dts/qcom/shikra.dtsi | 1679 +++++++++++++++++++-
7 files changed, 1918 insertions(+), 20 deletions(-)
---
base-commit: 6e845bcb78c95af935094040bd4edc3c2b6dd784
change-id: 20260525-shikra-dt-m1-082dec382e7f
prerequisite-change-id: 20260511-shikra-dt-d75d97454646:v4
prerequisite-patch-id: 3a689e8dda5fd2755b689d94d095806b3f2e6eed
prerequisite-patch-id: 2acc300a68ed8c5364fb5f2f7d28fc0d56ab07bf
prerequisite-patch-id: 2357cac636e019eaf14d6a493a1c72bca56fe405
prerequisite-patch-id: 2885f299e711582da312ca9d13983d296a3dd5dc
prerequisite-patch-id: 91af5f3c01e766a53ce8de69aa21847a2d6bbbf8
prerequisite-change-id: 20260513-shikra-rproc-0da355c56c69:v3
prerequisite-patch-id: 39475cddaf673b2cbbae703165a782916f199885
prerequisite-patch-id: 6f7f265abfbdffdc0a1fdc5a7e08929e4eec5b7a
prerequisite-change-id: 20260512-tsens_binding-9af005e4b32e:v1
prerequisite-patch-id: 35141047f44b4845f9d94618bcf26ec58ab4a0b2
prerequisite-change-id: 20260524-shikra_epss_l3-522afe4fb8f5:v3
prerequisite-patch-id: b5d7f75df02fde56181f576a936baf09d0a72276
prerequisite-patch-id: 3ce52e07ae57139c2e2b71a29ed7d7250f6fcc87
Best regards,
--
Komal Bajaj <komal.bajaj@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v3 10/10] arm64: dts: qcom: shikra: Enable Bluetooth and WiFi on EVK boards
From: Komal Bajaj @ 2026-06-08 13:00 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio, linux-arm-msm, dmaengine, devicetree, linux-kernel,
linux-pm, Yepuri Siddu, Miaoqing Pan
In-Reply-To: <j2l7ijr56b33uru53wiyhjkd66pxusxopr4c7xmztlqfnztha3@xp6ciwnngcv2>
On 6/6/2026 6:15 PM, Dmitry Baryshkov wrote:
> On Mon, Jun 01, 2026 at 06:25:12PM +0530, Komal Bajaj wrote:
>> Enable Bluetooth and WiFi connectivity on Shikra CQM, CQS and IQS
>> EVK boards using the WCN3988 combo chip.
>>
>> For Bluetooth, enable uart8 and add WCN3988 Bluetooth node with
>> board-specific regulator supplies across CQM, CQS and IQS Shikra
>> EVK boards.
>>
>> For WiFi, introduce the wcn3990-wifi hardware node in shikra.dtsi
>> with register space, interrupts, IOMMU configuration and reserved
>> memory. The node is kept disabled by default and enabled per-board
>> with the appropriate PMIC supply connections and calibration variant
>> selection.
>>
>> Co-developed-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
>> Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
>> Co-developed-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
>> Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
>> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 59 +++++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 59 +++++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 15 +++++++
>> arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 67 +++++++++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/shikra.dtsi | 23 ++++++++++
>> 5 files changed, 223 insertions(+)
>>
>> +
>> +&wifi {
>> + vdd-0.8-cx-mx-supply = <&pm4125_l7>;
>> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
>> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
>> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
>> + qcom,calibration-variant = "Shikra_EVK";
>> + firmware-name = "cq2390";
> firmware-name = "shikra";
ACK. I will update the name in next revision.
>
>> +
>> + status = "okay";
>> +};
>> +
> [...]
>
>> +&wifi {
>> + vdd-0.8-cx-mx-supply = <&pm4125_l7>;
>> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
>> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
>> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
>> + qcom,calibration-variant = "Shikra_EVK";
> I hope this means that calibration files are common across the boards.
Yes, it is.
Thanks
Komal
>
>> + firmware-name = "cq2390";
> firmware-name = "shikra";
>
>> +
>> + status = "okay";
>> +};
>
> [...]
>
>> +
>> +&wifi {
>> + vdd-0.8-cx-mx-supply = <&pm8150_s4>;
>> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
>> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
>> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
>> + qcom,calibration-variant = "Shikra_EVK";
>> + firmware-name = "cq2390";
> firmware-name = "shikra";
>> +
>> + status = "okay";
>> +};
^ permalink raw reply
* Re: [PATCH v3 08/10] arm64: dts: qcom: shikra: Enable CDSP, LPAICP and MPSS on EVK boards
From: Komal Bajaj @ 2026-06-08 12:54 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio, linux-arm-msm, dmaengine, devicetree, linux-kernel,
linux-pm, Bibek Kumar Patro
In-Reply-To: <ykcbo7dkl2rrjdzutpwsc3wmnub5r7h3zuspxiyh5v432whb65@sbaar24glpta>
On 6/6/2026 6:02 PM, Dmitry Baryshkov wrote:
> On Mon, Jun 01, 2026 at 06:25:10PM +0530, Komal Bajaj wrote:
>> From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
>>
>> Enable CDSP, LPAICP and MPSS for Qualcomm's Shikra CQM, CQS and
>> IQS EVK board.
>>
>> Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
>> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 19 +++++++++++++++++++
>> arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 19 +++++++++++++++++++
>> arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 19 +++++++++++++++++++
>> 3 files changed, 57 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
>> index 0a52ab9b7a4c..b112b21b1d79 100644
>> --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
>> +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
>> @@ -23,6 +23,25 @@ chosen {
>> };
>> };
>>
>> +&remoteproc_cdsp {
>> + firmware-name = "qcom/shikra/cdsp.mbn";
>> +
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_lpaicp {
>> + firmware-name = "qcom/shikra/lpaicp.mbn",
>> + "qcom/shikra/lpaicp_dtb.mbn";
>> +
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_mpss {
>> + firmware-name = "qcom/shikra/cqm/qdsp6sw.mbn";
> qcom/shikra/qdsp6sw.mbn
>
>> +
>> + status = "okay";
>> +};
>> +
>> &sdhc_1 {
>> vmmc-supply = <&pm4125_l20>;
>> vqmmc-supply = <&pm4125_l14>;
>> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
>> index b3f19a64d7ae..e62ba5aef71f 100644
>> --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
>> +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
>> @@ -23,6 +23,25 @@ chosen {
>> };
>> };
>>
>> +&remoteproc_cdsp {
>> + firmware-name = "qcom/shikra/cdsp.mbn";
>> +
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_lpaicp {
>> + firmware-name = "qcom/shikra/lpaicp.mbn",
>> + "qcom/shikra/lpaicp_dtb.mbn";
>> +
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_mpss {
>> + firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn";
> qcom/shikra/qdsp6sw_nm.mbn
We cannot change the firmware name, as our vendor builds and internal
tooling depend on the same naming convention for all three Shikra
variants. This is also why the binaries are placed under different paths.
Thanks
Komal
>
>> +
>> + status = "okay";
>> +};
>> +
>> &sdhc_1 {
>> vmmc-supply = <&pm4125_l20>;
>> vqmmc-supply = <&pm4125_l14>;
>> diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
>> index 3003a47bd759..727809430fd1 100644
>> --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
>> +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
>> @@ -23,6 +23,25 @@ chosen {
>> };
>> };
>>
>> +&remoteproc_cdsp {
>> + firmware-name = "qcom/shikra/cdsp.mbn";
>> +
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_lpaicp {
>> + firmware-name = "qcom/shikra/lpaicp.mbn",
>> + "qcom/shikra/lpaicp_dtb.mbn";
>> +
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_mpss {
>> + firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn";
> qcom/shikra/qdsp6sw_nm.mbn
>
>> +
>> + status = "okay";
>> +};
>> +
>> &sdhc_1 {
>> vmmc-supply = <&pm8150_l17>;
>> vqmmc-supply = <&pm8150_s4>;
>>
>> --
>> 2.34.1
>>
^ permalink raw reply
* Re: [PATCH RESEND] dmaengine: tegra: Fix burst size calculation
From: Vinod Koul @ 2026-06-08 12:14 UTC (permalink / raw)
To: ldewangan, jonathanh, akhilrajeev, Frank.Li, thierry.reding,
digetx, pkunapuli, dmaengine, linux-tegra, linux-kernel,
Kartik Rajput
Cc: stable, Frank Li
In-Reply-To: <20260422064134.1323610-1-kkartik@nvidia.com>
On Wed, 22 Apr 2026 12:11:34 +0530, Kartik Rajput wrote:
> Currently, the Tegra GPC DMA hardware requires the transfer length to
> be a multiple of the max burst size configured for the channel. When a
> client requests a transfer where the length is not evenly divisible by
> the configured max burst size, the DMA hangs with partial burst at
> the end.
>
> Fix this by reducing the burst size to the largest power-of-2 value
> that evenly divides the transfer length. For example, a 40-byte
> transfer with a 16-byte max burst will now use an 8-byte burst
> (40 / 8 = 5 complete bursts) instead of causing a hang.
>
> [...]
Applied, thanks!
[1/1] dmaengine: tegra: Fix burst size calculation
commit: 4651df83b6c796daead3447e8fd874322918ee4f
Best regards,
--
~Vinod
^ permalink raw reply
* Re: [PATCH v4 0/4] dmaengine: dma-axi-dmac: Some memory related fixes
From: Vinod Koul @ 2026-06-08 12:13 UTC (permalink / raw)
To: dmaengine, linux-kernel, Nuno Sá; +Cc: Lars-Peter Clausen, Frank Li
In-Reply-To: <20260424-dma-dmac-handle-vunmap-v4-0-90f43412fdc0@analog.com>
On Fri, 24 Apr 2026 18:40:13 +0100, Nuno Sá wrote:
> Here it goes v3. Given there are some discussions about adding devlinks
> in damengine, I dropped the patch implementing the .device_release() for
> now.
>
>
Applied, thanks!
[1/4] dmaengine: Fix possible use after free
commit: 92f853f0645aebf1d05d333e97ab7c342ace1892
[2/4] dmaengine: dma-axi-dmac: Properly free struct axi_dmac_desc
commit: 4910ce1b3b35687bb2a5e742c4bfbea3c647c980
[3/4] dmaengine: dma-axi-dmac: Drop struct clk from main struct
commit: a725ac2055271fe8123fa854bfeff6e349f7cf0e
[4/4] dmaengine: dma-axi-dmac: use DMA pool to manange DMA descriptor
commit: 9e942c8579130e62734c14338e9f451780669164
Best regards,
--
~Vinod
^ permalink raw reply
* Re: [PATCH] dma: iop32x-adma: Remove a leftover header file
From: Vinod Koul @ 2026-06-08 12:13 UTC (permalink / raw)
To: Arnd Bergmann, Vladimir Zapolskiy; +Cc: linux-arm-kernel, dmaengine
In-Reply-To: <20260114051508.3908807-1-vz@mleia.com>
On Wed, 14 Jan 2026 07:14:58 +0200, Vladimir Zapolskiy wrote:
> The Intel IOPx3xx platform was completely removed in commit b91a69d162aa
> ("ARM: iop32x: remove the platform"), and it'd be safe to remove an unused
> and leftover platform data specific header file dma-iop32x.h also.
>
>
Applied, thanks!
[1/1] dma: iop32x-adma: Remove a leftover header file
commit: b2d44b3ea95e10315559d8deedd8af2977c7f534
Best regards,
--
~Vinod
^ permalink raw reply
* Re: (subset) [PATCH 0/4] dmaengine: dw-edma: Fix probe paths and register races
From: Vinod Koul @ 2026-06-08 12:13 UTC (permalink / raw)
To: Manivannan Sadhasivam, Frank Li, Gustavo Pimentel, Koichiro Den
Cc: dmaengine, linux-kernel
In-Reply-To: <20260521142153.2957432-1-den@valinux.co.jp>
On Thu, 21 May 2026 23:21:49 +0900, Koichiro Den wrote:
> This series fixes pre-existing dw-edma issues flagged by Sashiko in:
> https://lore.kernel.org/dmaengine/20260521063115.2842238-1-den@valinux.co.jp/
>
> Note: Patch 4 was based on a patch Frank posted in January:
> https://lore.kernel.org/dmaengine/20260109-edma_ll-v2-1-5c0b27b2c664@nxp.com/
> Since it has not been merged, I included it here. Frank, please let me
> know if you prefer a different handling.
>
> [...]
Applied, thanks!
[2/4] dmaengine: dw-edma-pcie: Reject devices without driver data
commit: 11d7cfe0c119691b2dafbb699bbca90258c678aa
[4/4] dmaengine: dw-edma: Add spinlock to protect DONE_INT_MASK and ABORT_INT_MASK
commit: 8ffba0171c6bbce5f093c6dba5a02c0805b31203
Best regards,
--
~Vinod
^ permalink raw reply
* Re: [PATCH v4 0/2] Add DMA ACK signal routing for RZ/V2H family
From: Vinod Koul @ 2026-06-08 12:13 UTC (permalink / raw)
To: tglx, John Madieu
Cc: Frank.Li, claudiu.beznea.uj, biju.das.jz, geert+renesas,
cosmin-gabriel.tanislav.xa, dmaengine, linux-kernel, john.madieu
In-Reply-To: <20260525110750.4020112-1-john.madieu.xa@bp.renesas.com>
On Mon, 25 May 2026 11:07:48 +0000, John Madieu wrote:
> Some peripherals on RZ/V2H, RZ/V2N, and RZ/G3E SoCs require explicit
> DMA ACK signal routing through the ICU for level-based DMA handshaking.
>
> Rather than encoding the ACK signal number as a second DMA specifier
> cell, derive it in-driver from the MID/RID request number using
> arithmetic formulas based on ICU Table 4.6-28 (3 linear peripheral
> groups). It must also be noted that DMA ack register is located in
> the ICU block
>
> [...]
Applied, thanks!
[1/2] irqchip/renesas-rzv2h: Add DMA ACK signal routing support
commit: 5d596b9139f59ce412f41283baadaf809936eaf4
[2/2] dma: sh: rz-dmac: Add DMA ACK signal routing support
commit: c0a207898fca8cbb4fad0da1e950d477b6afbf64
Best regards,
--
~Vinod
^ permalink raw reply
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