Re: [PATCH 5/6] dmaengine: qcom: gpi: Add QSPI protocol support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found no new issues
in this patch, but noticed 1 related pre-existing issue it does not
introduce:
- [Critical] dmaengine: qcom: gpi: endianness bug in
  gpi_create_i2c_tre() [1]
--

commit 9cdfe35f34d7a7a0d6e8622961798e1c9733ec6f
Author: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>

dmaengine: qcom: gpi: Add QSPI protocol support

This commit adds QSPI protocol support to the Qualcomm GPI DMA driver,
including QSPI transfer modes, dummy cycles, and sequential TX-then-RX
transactions.

> diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c
> index a5055a6273af6..487e023287aa1 100644
> --- a/drivers/dma/qcom/gpi.c
> +++ b/drivers/dma/qcom/gpi.c
[ ... ]
> @@ -1736,7 +1742,12 @@ static int gpi_create_spi_tre(struct gchan *chan, struct gpi_desc *desc,
>  		tre = &desc->tre[tre_idx];
>  		tre_idx++;
>  
> -		tre->dword[0] = u32_encode_bits(spi->fragmentation, TRE_SPI_GO_FRAG);
> +		if (chan->protocol == QCOM_GPI_QSPI) {
> +			tre->dword[0] = u32_encode_bits(spi->fragmentation, TRE_QSPI_GO_FRAG);
> +			tre->dword[0] |= u32_encode_bits(spi->qspi_mode, TRE_QSPI_GO_MODE);
> +		} else {
> +			tre->dword[0] = u32_encode_bits(spi->fragmentation, TRE_SPI_GO_FRAG);
> +		}
>  		tre->dword[0] |= u32_encode_bits(spi->cs, TRE_SPI_GO_CS);
>  		tre->dword[0] |= u32_encode_bits(spi->cmd, TRE_SPI_GO_CMD);

[Severity: Critical]
This problem wasn't introduced by this patch, but should tre->dword[] be
written with cpu_to_le32() in gpi_create_spi_tre() and gpi_create_i2c_tre()
[1]?

Both functions populate tre->dword[] using host-endian values from
u32_encode_bits(), lower_32_bits(), and upper_32_bits():

drivers/dma/qcom/gpi.c:gpi_create_spi_tre() {
    ...
		tre->dword[0] = lower_32_bits(address);
		tre->dword[1] = upper_32_bits(address);

		tre->dword[2] = u32_encode_bits(len, TRE_DMA_LEN);
		tre->dword[3] = u32_encode_bits(TRE_TYPE_DMA, TRE_FLAGS_TYPE);
    ...
}

On big-endian hosts, the hardware receives byte-swapped descriptors, causing
DMA transfers to use corrupted configuration fields and invalid physical
addresses.

[1] https://sashiko.dev/#/bug/linux-b28be1ac-c36c-4aa8-a76a-58a19eaef473

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261106-qspi_upstream_series-v1-0-21f43042dd60@oss.qualcomm.com?part=5