RE: [PATCH v2 11/20] net/txgbe: fix traffic class priority configuration

["Zaiyu Wang" <zaiyuwang@trustnetic.com>]

> -----Original Message-----
> From: Stephen Hemminger <stephen@networkplumber.org>
> Sent: Wednesday, April 29, 2026 11:12 PM
> To: Zaiyu Wang <zaiyuwang@trustnetic.com>; Zaiyu Wang
> <zaiyuwang@trustnetic.com>
> Cc: dev@dpdk.org; stable@dpdk.org; Jiawen Wu <jiawenwu@trustnetic.com>;
> Ferruh Yigit <ferruh.yigit@amd.com>; dev@dpdk.org; stable@dpdk.org; Jiawen
> Wu <jiawenwu@trustnetic.com>; Ferruh Yigit <ferruh.yigit@amd.com>
> Subject: Re: [PATCH v2 11/20] net/txgbe: fix traffic class priority configuration
> 
> On Wed, 29 Apr 2026 18:25:05 +0800
> Zaiyu Wang <zaiyuwang@trustnetic.com> wrote:
> 
> > After applying the following testpmd command, 802.1Q packets with
> > specific priorities were not properly directed to the corresponding traffic classes:
> >     port config 0 dcb vt off 4 pfc off
> >
> > The old driver had two issues:
> > 1. The hardware uses a 4-bit mapping register per traffic class for
> >    priority-to-TC mapping, but the driver incorrectly configured it
> >    as 3 bits.
> > 2. The DCB TX configuration mistakenly wrote to the RX register.
> >
> > Fix both issues, ensuring that tc-prio mapping works as expected.
> >
> > Fixes: 8bdc7882f376 ("net/txgbe: support DCB")
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
> > ---
> 
> AI review spotted issues:
> 
> Error: The fix is incomplete. The same priority-to-TC layout is also written in
> drivers/net/txgbe/txgbe_rxtx.c around line 3380 in txgbe_vmdq_dcb_configure():
> for (i = 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++)
> 	/*
> 	 * mapping is done with 3 bits per priority,
> 	 * so shift by i*3 each time
> 	 */
> 	queue_mapping |= ((cfg->dcb_tc[i] & 0x07) << (i * 3));
> 
> wr32(hw, TXGBE_RPUP2TC, queue_mapping);
> This writes the same TXGBE_RPUP2TC register (0x019008) the patch is fixing,
> using a hardcoded i*3 shift and a comment claiming 3 bits per priority. After this
> patch, txgbe_dcb_config_rx_arbiter_raptor() encodes priorities at 4-bit positions
> (via the updated TXGBE_RPUP2TC_UP_SHIFT=4), but txgbe_vmdq_dcb_configure()
> still uses 3-bit positions. The VMDQ+DCB path will produce a wrong tc-prio
> mapping. txgbe_vmdq_dcb_configure() needs the same fix (use
> TXGBE_RPUP2TC_UP_SHIFT and update the comment).
> Warning: TXGBE_DCBUP2TC_DEC and TXGBE_DCBUP2TC_MAP are now
> inconsistent. After this patch:
> #define TXGBE_DCBUP2TC_MAP(tc, v)     LS(v, 4 * (tc), 0x7)
> #define TXGBE_DCBUP2TC_DEC(tc, r)     RS(r, 3 * (tc), 0x7)
> DEC will not decode what MAP encoded for any tc > 0. TXGBE_DCBUP2TC_DEC
> isn't currently used in tree, so this is not a runtime bug, but it's a latent trap. Either
> update DEC to also use 4*(tc), or remove DEC since it has no callers.
> 
Hi Stephen,
Thank you for the thorough AI‑assisted review. I really appreciate it.
I have addressed all the issues you raised, and an updated patch set will be sent shortly.