[PATCH] net/mlx5: fix offset handling in mlx5_aso_cnt_sq_enqueue_burst

[PATCH] net/mlx5: fix offset handling in mlx5_aso_cnt_sq_enqueue_burst

[Mohand Alrasheed]

From 9ca4302dd93461a7b01ad05af82ee2bcadf47675 Mon Sep 17 00:00:00 2001
From: Mohand Alrasheed <mrasheed@wirefilter.com>
Date: Mon, 5 Jan 2026 15:44:25 +0300
Subject: [PATCH] net/mlx5: fix offset handling in
 mlx5_aso_cnt_sq_enqueue_burst

mlx5_aso_cnt_sq_enqueue_burst() selects the ASO counter block using
dcs_id_base/4 and ignores the batch offset. This causes every batch to
target the first counter block, leading to counter aliasing (e.g. 2^16
matches 0).

This patch selects the counter block using the offset-adjusted index.

Reproducible example: https://github.com/Hawzen/rte-flow-async-profiling/blob/5e654e3a8a0414a5fa8ed43274195f180760f0b5/examples/flow_filtering/reproduce.md

Fixes: 4d368e1da3a453cbcac620e8844c0300b2f45cfa
Cc: jackmin@nvidia.com
Cc: stable@dpdk.org
---
 drivers/net/mlx5/mlx5_flow_aso.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/mlx5/mlx5_flow_aso.c b/drivers/net/mlx5/mlx5_flow_aso.c
index feca8c3e89..a232289024 100644
--- a/drivers/net/mlx5/mlx5_flow_aso.c
+++ b/drivers/net/mlx5/mlx5_flow_aso.c
@@ -1877,6 +1877,7 @@ mlx5_aso_cnt_sq_enqueue_burst(struct mlx5_hws_cnt_pool *cpool,
 	sq->elts[0].burst_size = max;
 	ctrl_gen_id = dcs_id_base;
 	ctrl_gen_id /= 4;
+	ctrl_gen_id += offset / 4;
 	do {
 		ccntid = upper_offset - max * 4;
 		wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
--
2.39.5

Re: [PATCH] net/mlx5: fix offset handling in mlx5_aso_cnt_sq_enqueue_burst

[Dariusz Sosnowski]

Hi,

On Mon, Jan 05, 2026 at 05:24:33PM +0300, Mohand Alrasheed wrote:
> 
> From 9ca4302dd93461a7b01ad05af82ee2bcadf47675 Mon Sep 17 00:00:00 2001
> From: Mohand Alrasheed <mrasheed@wirefilter.com>
> Date: Mon, 5 Jan 2026 15:44:25 +0300
> Subject: [PATCH] net/mlx5: fix offset handling in
>  mlx5_aso_cnt_sq_enqueue_burst
> 
> mlx5_aso_cnt_sq_enqueue_burst() selects the ASO counter block using
> dcs_id_base/4 and ignores the batch offset. This causes every batch to
> target the first counter block, leading to counter aliasing (e.g. 2^16
> matches 0).
> 
> This patch selects the counter block using the offset-adjusted index.
> 
> Reproducible example: https://github.com/Hawzen/rte-flow-async-profiling/blob/5e654e3a8a0414a5fa8ed43274195f180760f0b5/examples/flow_filtering/reproduce.md

Thank you very much for your contribution and reporting this issue.

There is in fact another issue with flow counter query logic
in mlx5_aso_cnt_query_one_dcs() function.
This function did not take into account a case when
mlx5_aso_cnt_sq_enqueue_burst() would query fewer counters than requested,
which could happen when available space in the queue is smaller lower than "n".

We have upstreamed a patch which addresses both of these issues: https://patches.dpdk.org/project/dpdk/patch/20260112172324.1523241-1-dsosnowski@nvidia.com/

Would you be able to test this patch locally on your side?

> 
> Fixes: 4d368e1da3a453cbcac620e8844c0300b2f45cfa
> Cc: jackmin@nvidia.com
> Cc: stable@dpdk.org
> ---
>  drivers/net/mlx5/mlx5_flow_aso.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/net/mlx5/mlx5_flow_aso.c b/drivers/net/mlx5/mlx5_flow_aso.c
> index feca8c3e89..a232289024 100644
> --- a/drivers/net/mlx5/mlx5_flow_aso.c
> +++ b/drivers/net/mlx5/mlx5_flow_aso.c
> @@ -1877,6 +1877,7 @@ mlx5_aso_cnt_sq_enqueue_burst(struct mlx5_hws_cnt_pool *cpool,
>  	sq->elts[0].burst_size = max;
>  	ctrl_gen_id = dcs_id_base;
>  	ctrl_gen_id /= 4;
> +	ctrl_gen_id += offset / 4;
>  	do {
>  		ccntid = upper_offset - max * 4;
>  		wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
> --
> 2.39.5
> 
> 

Best regards,
Dariusz Sosnowski

Re: [PATCH] net/mlx5: fix offset handling in mlx5_aso_cnt_sq_enqueue_burst

[Mohand Alrasheed]

Hi Dariusz,

Thanks for the update. I’ve responded with my feedback in the linked patch.

Best regards,
Mohand


-----Original Message-----
From: Dariusz <dsosnowski@nvidia.com>
To: Mohand <mrasheed@wirefilter.com>
Cc: dev <dev@dpdk.org>; viacheslavo <viacheslavo@nvidia.com>; bingz <bingz@nvidia.com>; orika <orika@nvidia.com>; suanmingm <suanmingm@nvidia.com>; matan <matan@nvidia.com>; jackmin <jackmin@nvidia.com>
Date: Monday, 12 January 2026 11:02 PM +03
Subject: Re: [PATCH] net/mlx5: fix offset handling in mlx5_aso_cnt_sq_enqueue_burst


Hi,

On Mon, Jan 05, 2026 at 05:24:33PM +0300, Mohand Alrasheed wrote:
> 
> From 9ca4302dd93461a7b01ad05af82ee2bcadf47675 Mon Sep 17 00:00:00 2001
> From: Mohand Alrasheed <mrasheed@wirefilter.com>
> Date: Mon, 5 Jan 2026 15:44:25 +0300
> Subject: [PATCH] net/mlx5: fix offset handling in
>  mlx5_aso_cnt_sq_enqueue_burst
> 
> mlx5_aso_cnt_sq_enqueue_burst() selects the ASO counter block using
> dcs_id_base/4 and ignores the batch offset. This causes every batch to
> target the first counter block, leading to counter aliasing (e.g. 2^16
> matches 0).
> 
> This patch selects the counter block using the offset-adjusted index.
> 
> Reproducible example: https://github.com/Hawzen/rte-flow-async-profiling/blob/5e654e3a8a0414a5fa8ed43274195f180760f0b5/examples/flow_filtering/reproduce.md

Thank you very much for your contribution and reporting this issue.

There is in fact another issue with flow counter query logic
in mlx5_aso_cnt_query_one_dcs() function.
This function did not take into account a case when
mlx5_aso_cnt_sq_enqueue_burst() would query fewer counters than requested,
which could happen when available space in the queue is smaller lower than "n".

We have upstreamed a patch which addresses both of these issues: https://patches.dpdk.org/project/dpdk/patch/20260112172324.1523241-1-dsosnowski@nvidia.com/

Would you be able to test this patch locally on your side?

> 
> Fixes: 4d368e1da3a453cbcac620e8844c0300b2f45cfa
> Cc: jackmin@nvidia.com
> Cc: stable@dpdk.org
> ---
>  drivers/net/mlx5/mlx5_flow_aso.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/net/mlx5/mlx5_flow_aso.c b/drivers/net/mlx5/mlx5_flow_aso.c
> index feca8c3e89..a232289024 100644
> --- a/drivers/net/mlx5/mlx5_flow_aso.c
> +++ b/drivers/net/mlx5/mlx5_flow_aso.c
> @@ -1877,6 +1877,7 @@ mlx5_aso_cnt_sq_enqueue_burst(struct mlx5_hws_cnt_pool *cpool,
>  	sq->elts[0].burst_size = max;
>  	ctrl_gen_id = dcs_id_base;
>  	ctrl_gen_id /= 4;
> +	ctrl_gen_id += offset / 4;
>  	do {
>  		ccntid = upper_offset - max * 4;
>  		wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
> --
> 2.39.5
> 
> 

Best regards,
Dariusz Sosnowski