From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Monjalon Subject: [PATCH] spinlock: fix atomic and out of order execution Date: Sat, 21 Dec 2013 00:37:36 +0100 Message-ID: <1387582656-1892-1-git-send-email-thomas.monjalon@6wind.com> To: dev-VfR2kkLFssw@public.gmane.org Return-path: List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" From: Damien Millescamps Add lock prefix before xchg instructions in order to be atomic and flush speculative values to ensure effective execution order (as an acquire barrier). MPLOCKED is a "lock" in multicore case. Signed-off-by: Damien Millescamps Signed-off-by: Thomas Monjalon --- lib/librte_eal/common/include/rte_spinlock.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/lib/librte_eal/common/include/rte_spinlock.h b/lib/librte_eal/common/include/rte_spinlock.h index f7a245a..8edb971 100644 --- a/lib/librte_eal/common/include/rte_spinlock.h +++ b/lib/librte_eal/common/include/rte_spinlock.h @@ -51,6 +51,7 @@ extern "C" { #endif +#include #include #ifdef RTE_FORCE_INTRINSICS #include @@ -93,7 +94,7 @@ rte_spinlock_lock(rte_spinlock_t *sl) int lock_val = 1; asm volatile ( "1:\n" - "xchg %[locked], %[lv]\n" + MPLOCKED "xchg %[locked], %[lv]\n" "test %[lv], %[lv]\n" "jz 3f\n" "2:\n" @@ -124,7 +125,7 @@ rte_spinlock_unlock (rte_spinlock_t *sl) #ifndef RTE_FORCE_INTRINSICS int unlock_val = 0; asm volatile ( - "xchg %[locked], %[ulv]\n" + MPLOCKED "xchg %[locked], %[ulv]\n" : [locked] "=m" (sl->locked), [ulv] "=q" (unlock_val) : "[ulv]" (unlock_val) : "memory"); @@ -148,7 +149,7 @@ rte_spinlock_trylock (rte_spinlock_t *sl) int lockval = 1; asm volatile ( - "xchg %[locked], %[lockval]" + MPLOCKED "xchg %[locked], %[lockval]" : [locked] "=m" (sl->locked), [lockval] "=q" (lockval) : "[lockval]" (lockval) : "memory"); -- 1.7.10.4