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From: Chao Zhu <bjzhuc-vtt25B2cwJLQT0dZR+AlfA@public.gmane.org>
To: dev-VfR2kkLFssw@public.gmane.org
Subject: [PATCH 10/12] Add cache size define for IBM Power Architecture
Date: Fri, 26 Sep 2014 05:36:24 -0400	[thread overview]
Message-ID: <1411724186-8036-11-git-send-email-bjzhuc@cn.ibm.com> (raw)
In-Reply-To: <1411724186-8036-1-git-send-email-bjzhuc-vtt25B2cwJLQT0dZR+AlfA@public.gmane.org>

IBM Power architecture has different cache line size (128 bytes) than
x86 (64 bytes). This patch defines CACHE_LINE_SIZE to 128 bytes to
override the default value 64 bytes to support IBM Power Architecture.

Signed-off-by: Chao Zhu <bjzhuc-vtt25B2cwJLQT0dZR+AlfA@public.gmane.org>
---
 app/test/test_malloc.c      |    8 ++++----
 app/test/test_mbuf.c        |    2 +-
 mk/arch/powerpc/rte.vars.mk |    2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/app/test/test_malloc.c b/app/test/test_malloc.c
index ee34ca3..63e6b32 100644
--- a/app/test/test_malloc.c
+++ b/app/test/test_malloc.c
@@ -300,9 +300,9 @@ test_big_alloc(void)
 	size_t size =rte_str_to_size(MALLOC_MEMZONE_SIZE)*2;
 	int align = 0;
 #ifndef RTE_LIBRTE_MALLOC_DEBUG
-	int overhead = 64 + 64;
+	int overhead = CACHE_LINE_SIZE + CACHE_LINE_SIZE;
 #else
-	int overhead = 64 + 64 + 64;
+	int overhead = CACHE_LINE_SIZE + CACHE_LINE_SIZE + CACHE_LINE_SIZE;
 #endif
 
 	rte_malloc_get_socket_stats(socket, &pre_stats);
@@ -356,9 +356,9 @@ test_multi_alloc_statistics(void)
 #ifndef RTE_LIBRTE_MALLOC_DEBUG
 	int trailer_size = 0;
 #else
-	int trailer_size = 64;
+	int trailer_size = CACHE_LINE_SIZE;
 #endif
-	int overhead = 64 + trailer_size;
+	int overhead = CACHE_LINE_SIZE + trailer_size;
 
 	rte_malloc_get_socket_stats(socket, &pre_stats);
 
diff --git a/app/test/test_mbuf.c b/app/test/test_mbuf.c
index 21024e7..03da329 100644
--- a/app/test/test_mbuf.c
+++ b/app/test/test_mbuf.c
@@ -832,7 +832,7 @@ test_failing_mbuf_sanity_check(void)
 static int
 test_mbuf(void)
 {
-	RTE_BUILD_BUG_ON(sizeof(struct rte_mbuf) != 64);
+	RTE_BUILD_BUG_ON(sizeof(struct rte_mbuf) != CACHE_LINE_SIZE);
 
 	/* create pktmbuf pool if it does not exist */
 	if (pktmbuf_pool == NULL) {
diff --git a/mk/arch/powerpc/rte.vars.mk b/mk/arch/powerpc/rte.vars.mk
index 363fcd1..dfdeaea 100644
--- a/mk/arch/powerpc/rte.vars.mk
+++ b/mk/arch/powerpc/rte.vars.mk
@@ -32,7 +32,7 @@
 ARCH  ?= powerpc
 CROSS ?=
 
-CPU_CFLAGS  ?= -m64
+CPU_CFLAGS  ?= -m64 -DCACHE_LINE_SIZE=128
 CPU_LDFLAGS ?=
 CPU_ASFLAGS ?= -felf64
 
-- 
1.7.1

  parent reply	other threads:[~2014-09-26  9:36 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-26  9:36 [PATCH 00/12] Patches for DPDK to support Power architecture Chao Zhu
     [not found] ` <1411724186-8036-1-git-send-email-bjzhuc-vtt25B2cwJLQT0dZR+AlfA@public.gmane.org>
2014-09-26  9:36   ` [PATCH 01/12] Add compiling definations for IBM " Chao Zhu
2014-09-26  9:36   ` [PATCH 02/12] Add atomic operations " Chao Zhu
     [not found]     ` <1411724186-8036-3-git-send-email-bjzhuc-vtt25B2cwJLQT0dZR+AlfA@public.gmane.org>
2014-09-29  6:16       ` Hemant-KZfg59tc24xl57MIdRCFDg
     [not found]         ` <f2004db873754dd5af7be40c6883473e-swgC6WJTr6E3qekZfdyv35wN6zqB+hSMnBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2014-09-29  6:41           ` Chao CH Zhu
2014-10-16  0:39       ` Ananyev, Konstantin
     [not found]         ` <2601191342CEEE43887BDE71AB97725821393C8F-kPTMFJFq+rEu0RiL9chJVbfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2014-10-16  3:14           ` Chao CH Zhu
     [not found]             ` <OFCD69120A.E4F3D7D4-ON48257D73.0011507B-48257D73.0011E4AC-vtt25B2cwJLQT0dZR+AlfA@public.gmane.org>
2014-10-16  9:42               ` Richardson, Bruce
     [not found]                 ` <59AF69C657FD0841A61C55336867B5B03441F561-kPTMFJFq+rELt2AQoY/u9bfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2014-10-16 11:04                   ` Ananyev, Konstantin
     [not found]             ` <2601191342CEEE43887BDE71AB97725821393F5D@IRSMSX105.ger.corp.intel.com>
     [not found]               ` <2601191342CEEE43887BDE71AB97725821393F5D-kPTMFJFq+rEu0RiL9chJVbfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2014-10-16 10:59                 ` Ananyev, Konstantin
2014-09-26  9:36   ` [PATCH 03/12] Add byte order " Chao Zhu
2014-09-26  9:36   ` [PATCH 04/12] Add CPU cycle " Chao Zhu
2014-09-26  9:36   ` [PATCH 05/12] Add prefetch operation " Chao Zhu
2014-09-26  9:36   ` [PATCH 06/12] Add spinlock " Chao Zhu
2014-09-26  9:36   ` [PATCH 07/12] Add vector memcpy " Chao Zhu
2014-09-26  9:36   ` [PATCH 08/12] Add CPU flag checking " Chao Zhu
2014-09-26  9:36   ` [PATCH 09/12] Remove iopl operation " Chao Zhu
     [not found]     ` <1411724186-8036-10-git-send-email-bjzhuc-vtt25B2cwJLQT0dZR+AlfA@public.gmane.org>
2014-10-06 22:03       ` Cyril Chemparathy
     [not found]         ` <543311C7.40906-kv+TWInifGbQT0dZR+AlfA@public.gmane.org>
2014-10-07 14:46           ` Ananyev, Konstantin
     [not found]             ` <2601191342CEEE43887BDE71AB97725821391202-kPTMFJFq+rEu0RiL9chJVbfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2014-10-13  2:33               ` Chao CH Zhu
2014-09-26  9:36   ` Chao Zhu [this message]
     [not found]     ` <1411724186-8036-11-git-send-email-bjzhuc-vtt25B2cwJLQT0dZR+AlfA@public.gmane.org>
2014-09-29  6:21       ` [PATCH 10/12] Add cache size define for IBM Power Architecture Hemant-KZfg59tc24xl57MIdRCFDg
     [not found]         ` <307e2643dd894afc9e53e0c3de74c32a-swgC6WJTr6E3qekZfdyv35wN6zqB+hSMnBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2014-09-29  6:40           ` Chao CH Zhu
2014-09-26  9:36   ` [PATCH 11/12] Add huge page sizes for IBM Power architecture Chao Zhu
2014-09-26  9:36   ` [PATCH 12/12] Add memory support for IBM Power Architecture Chao Zhu
2014-11-13 10:24   ` [PATCH 00/12] Patches for DPDK to support Power architecture Thomas Monjalon
2014-11-13 10:31     ` Chao Zhu

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