[PATCH 04/12] Add CPU cycle operations for IBM Power architecture

[Chao Zhu <bjzhuc-vtt25B2cwJLQT0dZR+AlfA@public.gmane.org>]

IBM Power architecture doesn't have TSC register to get CPU cycles. This
patch implements the time base register read instead of TSC register of
x86 on IBM Power architecture.

Signed-off-by: Chao Zhu <bjzhuc-vtt25B2cwJLQT0dZR+AlfA@public.gmane.org>
---
 .../common/include/powerpc/arch/rte_cycles_arch.h  |   67 ++++++++++++++++++++
 1 files changed, 67 insertions(+), 0 deletions(-)
 create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_cycles_arch.h

diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_cycles_arch.h b/lib/librte_eal/common/include/powerpc/arch/rte_cycles_arch.h
new file mode 100644
index 0000000..faae7a6
--- /dev/null
+++ b/lib/librte_eal/common/include/powerpc/arch/rte_cycles_arch.h
@@ -0,0 +1,67 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of IBM Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_CYCLES_ARCH_H_
+#define _RTE_CYCLES_ARCH_H_
+
+#include <stdint.h>
+
+/**
+ * Read the time base register.
+ *
+ * @return
+ *   The time base for this lcore.
+ */
+static inline uint64_t
+rte_arch_rdtsc(void)
+{
+	union {
+		uint64_t tsc_64;
+		struct {
+			uint32_t hi_32;
+			uint32_t lo_32;
+		};
+	} tsc;
+	uint32_t tmp;
+	asm volatile(
+			"0:\n"
+			"mftbu   %[hi32]\n"
+			"mftb    %[lo32]\n"
+			"mftbu   %[tmp]\n"
+			"cmpw    %[tmp],%[hi32]\n"
+			"bne     0b\n"
+			: [hi32] "=r"(tsc.hi_32), [lo32] "=r"(tsc.lo_32), [tmp] "=r"(tmp)
+		    );
+	return tsc.tsc_64;
+}
+#endif /* _RTE_CYCLES_ARCH_H_ */
+
-- 
1.7.1