From mboxrd@z Thu Jan 1 00:00:00 1970 From: Helin Zhang Subject: [PATCH 2/6] e1000: fill the hash key size Date: Thu, 4 Jun 2015 09:00:34 +0800 Message-ID: <1433379638-32715-3-git-send-email-helin.zhang@intel.com> References: <1433379638-32715-1-git-send-email-helin.zhang@intel.com> To: dev@dpdk.org Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 73AB25A9A for ; Thu, 4 Jun 2015 03:00:49 +0200 (CEST) In-Reply-To: <1433379638-32715-1-git-send-email-helin.zhang@intel.com> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The correct hash key size in bytes should be filled into the 'struct rte_eth_dev_info', to support querying it. Signed-off-by: Helin Zhang --- drivers/net/e1000/igb_ethdev.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c index e4b370d..7d388f3 100644 --- a/drivers/net/e1000/igb_ethdev.c +++ b/drivers/net/e1000/igb_ethdev.c @@ -68,6 +68,8 @@ #define IGB_DEFAULT_TX_HTHRESH 0 #define IGB_DEFAULT_TX_WTHRESH 0 +#define IGB_HKEY_MAX_INDEX 10 + /* Bit shift and mask */ #define IGB_4_BIT_WIDTH (CHAR_BIT / 2) #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t) @@ -1377,6 +1379,7 @@ eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) /* Should not happen */ break; } + dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t); dev_info->reta_size = ETH_RSS_RETA_SIZE_128; dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL; -- 1.9.3