From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tomasz Kulasek Subject: [PATCH] ixgbe: fix bad shift operation in ixgbe_set_pool_rx Date: Fri, 15 Apr 2016 15:39:09 +0200 Message-ID: <1460727549-4380-1-git-send-email-tomaszx.kulasek@intel.com> Cc: helin.zhang@intel.com, konstantin.ananyev@intel.com To: dev@dpdk.org Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 82F532C00 for ; Fri, 15 Apr 2016 15:39:17 +0200 (CEST) List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" CID 13193 (#1 of 1): Bad bit shift operation (BAD_SHIFT) large_shift: In expression 1 << pool, left shifting by more than 31 bits has undefined behavior. The shift amount, pool, is at least 32. This patch limits mask shift to be in range of 32 bit PFVFRE[1] register, for pool > 31. Fixes: fe3a45fd4104 ("ixgbe: add VMDq support") Signed-off-by: Tomasz Kulasek --- drivers/net/ixgbe/ixgbe_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c index 3f1ebc1..f676a64 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/ixgbe/ixgbe_ethdev.c @@ -4401,7 +4401,7 @@ ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on) addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2); reg = IXGBE_READ_REG(hw, addr); - val = bit1 << pool; + val = bit1 << (pool & 0x01F); if (on) reg |= val; -- 1.7.9.5