From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jasvinder Singh Subject: [PATCH v2] ip_pipeline: fix false cacheline sharing among threads Date: Sun, 12 Jun 2016 13:42:47 +0100 Message-ID: <1465735367-187704-1-git-send-email-jasvinder.singh@intel.com> References: <1465658356-59012-1-git-send-email-jasvinder.singh@intel.com> Cc: cristian.dumitrescu@intel.com To: dev@dpdk.org Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 6F02D2BBC for ; Sun, 12 Jun 2016 14:35:31 +0200 (CEST) In-Reply-To: <1465658356-59012-1-git-send-email-jasvinder.singh@intel.com> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In ip_pipeline app, the structure app_thread_data needs to be aligned to the cache line boundary as threads on different cpu cores are accessing fields of the app->thread_data and having this structure not aligned on cacheline boundary leads to false cacheline sharing. Fixes: 7f64b9c004aa ("examples/ip_pipeline: rework config file syntax") Signed-off-by: Jasvinder Singh Acked-by: Cristian Dumitrescu --- v2 - fix checkpatch error examples/ip_pipeline/app.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/ip_pipeline/app.h b/examples/ip_pipeline/app.h index 848244a..7611341 100644 --- a/examples/ip_pipeline/app.h +++ b/examples/ip_pipeline/app.h @@ -300,7 +300,7 @@ struct app_thread_data { uint64_t headroom_time; uint64_t headroom_cycles; double headroom_ratio; -}; +} __rte_cache_aligned; #ifndef APP_MAX_LINKS #define APP_MAX_LINKS 16 -- 2.5.5