From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chas Williams <3chas3@gmail.com> Subject: [PATCH 01/10] bnx2x: Set cache line based on build configuration Date: Mon, 11 Jul 2016 17:11:22 -0400 Message-ID: <1468271491-28510-1-git-send-email-3chas3@gmail.com> Cc: harish.patil@qlogic.com, Chas Williams <3chas3@gmail.com> To: dev@dpdk.org Return-path: Received: from mail-qt0-f194.google.com (mail-qt0-f194.google.com [209.85.216.194]) by dpdk.org (Postfix) with ESMTP id 3AFD2FE5 for ; Mon, 11 Jul 2016 23:11:42 +0200 (CEST) Received: by mail-qt0-f194.google.com with SMTP id q11so2313141qtb.2 for ; Mon, 11 Jul 2016 14:11:42 -0700 (PDT) List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Correctly hint the cache line size. Remove unused macros associated with the cache line size. Fixes: 540a211084a7 ("bnx2x: driver core") Signed-off-by: Chas Williams <3chas3@gmail.com> --- drivers/net/bnx2x/bnx2x.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h index 135a6eb..852ec94 100644 --- a/drivers/net/bnx2x/bnx2x.h +++ b/drivers/net/bnx2x/bnx2x.h @@ -302,10 +302,7 @@ struct bnx2x_device_type { /* TCP with Timestamp Option (32) + IPv6 (40) */ /* max supported alignment is 256 (8 shift) */ -#define BNX2X_RX_ALIGN_SHIFT 8 -/* FW uses 2 cache lines alignment for start packet and size */ -#define BNX2X_FW_RX_ALIGN_START (1 << BNX2X_RX_ALIGN_SHIFT) -#define BNX2X_FW_RX_ALIGN_END (1 << BNX2X_RX_ALIGN_SHIFT) +#define BNX2X_RX_ALIGN_SHIFT RTE_MAX(6, min(8, RTE_CACHE_LINE_SIZE_LOG2)) #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) -- 2.5.5