From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jeff Guo Subject: [PATCH v2 2/2] drivers/i40e: Add FD PCTYPE translation for device x722 Date: Wed, 7 Sep 2016 05:38:40 -0400 Message-ID: <1473241120-115147-1-git-send-email-jia.guo@intel.com> References: <1472203505-76527-2-git-send-email-jia.guo@intel.com> Cc: dev@dpdk.org, jia.guo@intel.com To: helin.zhang@intel.com, jingjing.wu@intel.com Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 653B68DA9 for ; Wed, 7 Sep 2016 11:35:22 +0200 (CEST) In-Reply-To: <1472203505-76527-2-git-send-email-jia.guo@intel.com> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In device x722, before the FD filter is programmed, the PCTYPE in the FD programming descriptor need to use GLQF_FD_PCTYPE table to translate into Second PCTYPE, that will let new PCTYPE compatible with original PCTYPE in FD filter. Signed-off-by: Jeff Guo --- drivers/net/i40e/i40e_ethdev.c | 11 +++++++++++ drivers/net/i40e/i40e_fdir.c | 17 +++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index aee8f40..183e742 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -7736,7 +7736,16 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw, PMD_DRV_LOG(ERR, "invalid flow_type input."); return -EINVAL; } + +#ifdef X722_SUPPORT + /* get translated pctype value in fd pctype register */ + pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw, + I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype( + conf->flow_type))); +#else pctype = i40e_flowtype_to_pctype(conf->flow_type); +#endif + ret = i40e_parse_input_set(&input_set, pctype, conf->field, conf->inset_size); if (ret) { @@ -7805,7 +7814,9 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf, PMD_DRV_LOG(ERR, "invalid flow_type input."); return -EINVAL; } + pctype = i40e_flowtype_to_pctype(conf->flow_type); + ret = i40e_parse_input_set(&input_set, pctype, conf->field, conf->inset_size); if (ret) { diff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c index f65c411..b32b7ec 100644 --- a/drivers/net/i40e/i40e_fdir.c +++ b/drivers/net/i40e/i40e_fdir.c @@ -664,7 +664,14 @@ i40e_fdir_configure(struct rte_eth_dev *dev) i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]); /* configure flex mask*/ for (i = 0; i < conf->nb_flexmasks; i++) { +#ifdef X722_SUPPORT + /* get translated pctype value in fd pctype register */ + pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw, + I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype( + conf->flex_mask[i].flow_type))); +#else pctype = i40e_flowtype_to_pctype(conf->flex_mask[i].flow_type); +#endif i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]); } @@ -1012,6 +1019,7 @@ i40e_add_del_fdir_filter(struct rte_eth_dev *dev, const struct rte_eth_fdir_filter *filter, bool add) { + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt; enum i40e_filter_pctype pctype; @@ -1044,7 +1052,16 @@ i40e_add_del_fdir_filter(struct rte_eth_dev *dev, PMD_DRV_LOG(ERR, "construct packet for fdir fails."); return ret; } + +#ifdef X722_SUPPORT + /* get translated pctype value in fd pctype register */ + pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw, + I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype( + filter->input.flow_type))); +#else pctype = i40e_flowtype_to_pctype(filter->input.flow_type); +#endif + ret = i40e_fdir_filter_programming(pf, pctype, filter, add); if (ret < 0) { PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).", -- 2.1.4