From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Subject: [PATCH 14/28] crypto/qat: use eal I/O device memory
	read/write API
Date: Wed, 14 Dec 2016 07:25:44 +0530
Message-ID: <1481680558-4003-15-git-send-email-jerin.jacob@caviumnetworks.com>
References: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
Mime-Version: 1.0
Content-Type: text/plain
Cc: <konstantin.ananyev@intel.com>, <thomas.monjalon@6wind.com>,
 <bruce.richardson@intel.com>, <jianbo.liu@linaro.org>,
 <viktorin@rehivetech.com>, Santosh Shukla
 <santosh.shukla@caviumnetworks.com>, Jerin Jacob
 <jerin.jacob@caviumnetworks.com>, John Griffin <john.griffin@intel.com>,
 Fiona Trahe <fiona.trahe@intel.com>, Deepak Kumar Jain
 <deepak.k.jain@intel.com>
To: <dev@dpdk.org>
Return-path: <dev-bounces@dpdk.org>
Received: from NAM03-DM3-obe.outbound.protection.outlook.com
 (mail-dm3nam03on0064.outbound.protection.outlook.com [104.47.41.64])
 by dpdk.org (Postfix) with ESMTP id 2C7AB4AC7
 for <dev@dpdk.org>; Wed, 14 Dec 2016 02:58:47 +0100 (CET)
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <http://dpdk.org/ml/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://dpdk.org/ml/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <http://dpdk.org/ml/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>

From: Santosh Shukla <santosh.shukla@caviumnetworks.com>

Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix portability
issues across different architectures.

Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: John Griffin <john.griffin@intel.com>
CC: Fiona Trahe <fiona.trahe@intel.com>
CC: Deepak Kumar Jain <deepak.k.jain@intel.com>
---
 drivers/crypto/qat/qat_adf/adf_transport_access_macros.h | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h b/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h
index 47f1c91..a6e407d 100644
--- a/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h
+++ b/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h
@@ -47,14 +47,19 @@
 #ifndef ADF_TRANSPORT_ACCESS_MACROS_H
 #define ADF_TRANSPORT_ACCESS_MACROS_H
 
+#include <rte_io.h>
+
 /* CSR write macro */
-#define ADF_CSR_WR(csrAddr, csrOffset, val) \
-	(void)((*((volatile uint32_t *)(((uint8_t *)csrAddr) + csrOffset)) \
-			= (val)))
+#define ADF_CSR_WR(csrAddr, csrOffset, val) ({			\
+	rte_writel(val, (((uint8_t *)csrAddr) + csrOffset));	\
+})
 
 /* CSR read macro */
-#define ADF_CSR_RD(csrAddr, csrOffset) \
-	(*((volatile uint32_t *)(((uint8_t *)csrAddr) + csrOffset)))
+#define ADF_CSR_RD(csrAddr, csrOffset) ({			\
+	uint32_t __val;						\
+	__val = rte_readl(((uint8_t *)csrAddr) + csrOffset);	\
+	__val;							\
+})
 
 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
-- 
2.5.5