From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jerin Jacob Subject: [PATCH v5 04/29] eal/ppc64: define I/O device memory barriers for ppc64 Date: Wed, 18 Jan 2017 06:51:17 +0530 Message-ID: <1484702502-25451-5-git-send-email-jerin.jacob@caviumnetworks.com> References: <1484637244-7548-1-git-send-email-jerin.jacob@caviumnetworks.com> <1484702502-25451-1-git-send-email-jerin.jacob@caviumnetworks.com> Mime-Version: 1.0 Content-Type: text/plain Cc: , , , , , , Jerin Jacob , Chao Zhu To: Return-path: Received: from NAM03-BY2-obe.outbound.protection.outlook.com (mail-by2nam03on0042.outbound.protection.outlook.com [104.47.42.42]) by dpdk.org (Postfix) with ESMTP id 556B42E8B for ; Wed, 18 Jan 2017 02:22:30 +0100 (CET) In-Reply-To: <1484702502-25451-1-git-send-email-jerin.jacob@caviumnetworks.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The patch does not provide any functional change for ppc_64. I/O barriers are mapped to existing smp barriers. CC: Chao Zhu Signed-off-by: Jerin Jacob --- lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h index fb4fccb..150810c 100644 --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h @@ -87,6 +87,12 @@ extern "C" { #define rte_smp_rmb() rte_rmb() +#define rte_io_mb() rte_mb() + +#define rte_io_wmb() rte_wmb() + +#define rte_io_rmb() rte_rmb() + /*------------------------- 16 bit atomic operations -------------------------*/ /* To be compatible with Power7, use GCC built-in functions for 16 bit * operations */ -- 2.5.5