From mboxrd@z Thu Jan 1 00:00:00 1970 From: Qi Zhang Subject: [PATCH 16/25] net/i40e/base: add defines for flat NVM Date: Sun, 7 Jan 2018 22:43:26 -0500 Message-ID: <1515383015-28042-17-git-send-email-qi.z.zhang@intel.com> References: <1515383015-28042-1-git-send-email-qi.z.zhang@intel.com> Cc: dev@dpdk.org, jingjing.wu@intel.com, Qi Zhang To: beilei.xing@intel.com Return-path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 88D161B1DD for ; Mon, 8 Jan 2018 11:52:24 +0100 (CET) In-Reply-To: <1515383015-28042-1-git-send-email-qi.z.zhang@intel.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" New control bits were defined for flat NVM structure. One for pointing which NVM bank is currently used and one used as indicator of structure type. Signed-off-by: Qi Zhang --- drivers/net/i40e/base/i40e_type.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h index 056ca4d1d..a062816c6 100644 --- a/drivers/net/i40e/base/i40e_type.h +++ b/drivers/net/i40e/base/i40e_type.h @@ -1538,6 +1538,8 @@ struct i40e_hw_port_stats { #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) +#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) +#define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) /* Shadow RAM related */ #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 -- 2.14.1