From mboxrd@z Thu Jan 1 00:00:00 1970 From: Qi Zhang Subject: [PATCH 02/25] net/i40e/base: add capability macros Date: Sun, 7 Jan 2018 22:43:12 -0500 Message-ID: <1515383015-28042-3-git-send-email-qi.z.zhang@intel.com> References: <1515383015-28042-1-git-send-email-qi.z.zhang@intel.com> Cc: dev@dpdk.org, jingjing.wu@intel.com, Qi Zhang To: beilei.xing@intel.com Return-path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id D472F1B16A for ; Mon, 8 Jan 2018 11:52:10 +0100 (CET) In-Reply-To: <1515383015-28042-1-git-send-email-qi.z.zhang@intel.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add capability macros for 25G AOC/ACC PHYS. Signed-off-by: Qi Zhang --- drivers/net/i40e/base/i40e_type.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h index dca725afd..42b2d9166 100644 --- a/drivers/net/i40e/base/i40e_type.h +++ b/drivers/net/i40e/base/i40e_type.h @@ -351,6 +351,10 @@ struct i40e_phy_info { I40E_PHY_TYPE_OFFSET) #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \ I40E_PHY_TYPE_OFFSET) +#define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \ + I40E_PHY_TYPE_OFFSET) +#define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \ + I40E_PHY_TYPE_OFFSET) #define I40E_HW_CAP_MAX_GPIO 30 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 -- 2.14.1