From mboxrd@z Thu Jan 1 00:00:00 1970 From: Fiona Trahe Subject: [PATCH 25/30] crypto/qat: add lock around csr access and change logic Date: Fri, 6 Apr 2018 19:52:07 +0100 Message-ID: <1523040732-3290-26-git-send-email-fiona.trahe@intel.com> References: <1523040732-3290-1-git-send-email-fiona.trahe@intel.com> Cc: fiona.trahe@intel.com, tomaszx.jozwiak@intel.com To: dev@dpdk.org, pablo.de.lara.guarch@intel.com Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id E0CE81CEC7 for ; Fri, 6 Apr 2018 20:52:55 +0200 (CEST) In-Reply-To: <1523040732-3290-1-git-send-email-fiona.trahe@intel.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add lock around accesses to the arbiter CSR and use & instead of ^ as ^ not safe if arb_disable called when already disabled. Signed-off-by: Fiona Trahe --- drivers/crypto/qat/qat_qp.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/crypto/qat/qat_qp.c b/drivers/crypto/qat/qat_qp.c index cf89d8440..2e12f7c82 100644 --- a/drivers/crypto/qat/qat_qp.c +++ b/drivers/crypto/qat/qat_qp.c @@ -107,8 +107,10 @@ static int qat_queue_create(struct qat_pci_device *qat_dev, static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num, uint32_t *queue_size_for_csr); static void adf_configure_queues(struct qat_qp *queue); -static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr); -static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr); +static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr, + rte_spinlock_t *lock); +static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr, + rte_spinlock_t *lock); int qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data, @@ -234,7 +236,8 @@ int qat_qp_setup(struct qat_pci_device *qat_dev, } adf_configure_queues(qp); - adf_queue_arb_enable(&qp->tx_q, qp->mmap_bar_addr); + adf_queue_arb_enable(&qp->tx_q, qp->mmap_bar_addr, + &qat_dev->arb_csr_lock); snprintf(op_cookie_pool_name, RTE_RING_NAMESIZE, "%s%d_cookies_%s_qp%hu", @@ -300,7 +303,8 @@ int qat_qp_release(struct qat_qp **qp_addr) return -EAGAIN; } - adf_queue_arb_disable(&(qp->tx_q), qp->mmap_bar_addr); + adf_queue_arb_disable(&(qp->tx_q), qp->mmap_bar_addr, + &qp->qat_dev->arb_csr_lock); for (i = 0; i < qp->nb_descriptors; i++) rte_mempool_put(qp->op_cookie_pool, qp->op_cookies[i]); @@ -461,7 +465,8 @@ static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num, return -EINVAL; } -static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr) +static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr, + rte_spinlock_t *lock) { uint32_t arb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET + (ADF_ARB_REG_SLOT * @@ -469,12 +474,16 @@ static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr) uint32_t value; PMD_INIT_FUNC_TRACE(); + + rte_spinlock_lock(lock); value = ADF_CSR_RD(base_addr, arb_csr_offset); value |= (0x01 << txq->hw_queue_number); ADF_CSR_WR(base_addr, arb_csr_offset, value); + rte_spinlock_unlock(lock); } -static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr) +static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr, + rte_spinlock_t *lock) { uint32_t arb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET + (ADF_ARB_REG_SLOT * @@ -482,9 +491,12 @@ static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr) uint32_t value; PMD_INIT_FUNC_TRACE(); + + rte_spinlock_lock(lock); value = ADF_CSR_RD(base_addr, arb_csr_offset); - value ^= (0x01 << txq->hw_queue_number); + value &= ~(0x01 << txq->hw_queue_number); ADF_CSR_WR(base_addr, arb_csr_offset, value); + rte_spinlock_unlock(lock); } static void adf_configure_queues(struct qat_qp *qp) -- 2.13.6