From mboxrd@z Thu Jan  1 00:00:00 1970
From: Thomas Monjalon <thomas.monjalon-pdR9zngts4EAvxtiuMwx3w@public.gmane.org>
Subject: Re: [PATCH v3 3/5] ixgbe: Config PFVML2FLT register
Date: Thu, 06 Nov 2014 14:57:19 +0100
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References: <1414381533-30370-1-git-send-email-changchun.ouyang@intel.com>
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Cc: dev-VfR2kkLFssw@public.gmane.org
To: Ouyang Changchun <changchun.ouyang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
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Title would be more high level.
Example: "ixgbe: configure Rx mode for VMDQ"

2014-10-31 13:19, Ouyang Changchun:
> +	for (i = 0; i < (int)num_pools; i++) {
> +		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_UNTAG)
> +			vmolr |= IXGBE_VMOLR_AUPE;
> +		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_MC)
> +			vmolr |= IXGBE_VMOLR_ROMPE;
> +		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_UC)
> +			vmolr |= IXGBE_VMOLR_ROPE;
> +		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_BROADCAST)
> +			vmolr |= IXGBE_VMOLR_BAM;
> +		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_MULTICAST)
> +			vmolr |= IXGBE_VMOLR_MPE;
> +
> +		IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
> +	}

Please factorize code with ixgbe_set_pool_rx_mode() which is really similar.

-- 
Thomas