From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Rybchenko Subject: [PATCH 35/37] net/sfc/base: modify phy caps to indicate FEC request Date: Mon, 10 Sep 2018 10:33:34 +0100 Message-ID: <1536572016-18134-36-git-send-email-arybchenko@solarflare.com> References: <1536572016-18134-1-git-send-email-arybchenko@solarflare.com> Mime-Version: 1.0 Content-Type: text/plain Cc: Richard Houldsworth To: Return-path: Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 253E24CA7 for ; Mon, 10 Sep 2018 11:33:55 +0200 (CEST) Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us1.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id 0F7D5780055 for ; Mon, 10 Sep 2018 09:33:54 +0000 (UTC) In-Reply-To: <1536572016-18134-1-git-send-email-arybchenko@solarflare.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Richard Houldsworth The capability bits to request FEC modes are implicitly valid when the corresponding FEC mode is a supported capability. Drivers expect that it is only valid to advertise those capabilities explicitly marked as supported. The capabilities reported by firmware is modified with the implicit capabilities to present the explicit model to drivers. Signed-off-by: Richard Houldsworth Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/base/ef10_nic.c | 15 +++++++++++++++ drivers/net/sfc/base/efx_phy.c | 8 +------- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c index 0a2474f3e..b54cd3940 100644 --- a/drivers/net/sfc/base/ef10_nic.c +++ b/drivers/net/sfc/base/ef10_nic.c @@ -1772,6 +1772,21 @@ ef10_nic_board_cfg( if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) goto fail6; + /* + * Firmware with support for *_FEC capability bits does not + * report that the corresponding *_FEC_REQUESTED bits are supported. + * Add them here so that drivers understand that they are supported. + */ + if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_BASER_FEC)) + epp->ep_phy_cap_mask |= + (1u << EFX_PHY_CAP_BASER_FEC_REQUESTED); + if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_RS_FEC)) + epp->ep_phy_cap_mask |= + (1u << EFX_PHY_CAP_RS_FEC_REQUESTED); + if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_25G_BASER_FEC)) + epp->ep_phy_cap_mask |= + (1u << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED); + /* Obtain the default PHY advertised capabilities */ if ((rc = ef10_phy_get_link(enp, &els)) != 0) goto fail7; diff --git a/drivers/net/sfc/base/efx_phy.c b/drivers/net/sfc/base/efx_phy.c index 7c341e429..25059dfe1 100644 --- a/drivers/net/sfc/base/efx_phy.c +++ b/drivers/net/sfc/base/efx_phy.c @@ -192,11 +192,6 @@ efx_phy_adv_cap_get( } } -#define EFX_PHY_CAP_FEC_REQ_MASK \ - (1U << EFX_PHY_CAP_BASER_FEC_REQUESTED) | \ - (1U << EFX_PHY_CAP_RS_FEC_REQUESTED) | \ - (1U << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED) - __checkReturn efx_rc_t efx_phy_adv_cap_set( __in efx_nic_t *enp, @@ -210,8 +205,7 @@ efx_phy_adv_cap_set( EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); - /* Ignore don't care bits of FEC (FEC EFX_PHY_CAP_*_REQUESTED) */ - if ((mask & ~(epp->ep_phy_cap_mask | EFX_PHY_CAP_FEC_REQ_MASK)) != 0) { + if ((mask & ~epp->ep_phy_cap_mask) != 0) { rc = ENOTSUP; goto fail1; } -- 2.17.1