* [PATCH] ixgbe: fix ixgbe PCI access endian issue
@ 2015-02-12 1:19 xuelin.shi-KZfg59tc24xl57MIdRCFDg
[not found] ` <1423703990-29031-1-git-send-email-xuelin.shi-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
0 siblings, 1 reply; 3+ messages in thread
From: xuelin.shi-KZfg59tc24xl57MIdRCFDg @ 2015-02-12 1:19 UTC (permalink / raw)
To: thomas.monjalon-pdR9zngts4EAvxtiuMwx3w; +Cc: dev-VfR2kkLFssw
From: Xuelin Shi <xuelin.shi-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
ixgbe is little endian, but cpu maybe not.
add necessary conversions.
rte_cpu_to_le_32(...) for PCI write
rte_le_to_cpu_32(...) for PCI read.
Signed-off-by: Xuelin Shi <xuelin.shi-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h
index 2d40bfd..f8bfb3f 100644
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h
@@ -119,11 +119,11 @@ typedef int bool;
static inline uint32_t ixgbe_read_addr(volatile void* addr)
{
- return IXGBE_PCI_REG(addr);
+ return rte_le_to_cpu_32(IXGBE_PCI_REG(addr));
}
#define IXGBE_PCI_REG_WRITE(reg, value) do { \
- IXGBE_PCI_REG((reg)) = (value); \
+ IXGBE_PCI_REG((reg)) = (rte_cpu_to_le_32(value)); \
} while(0)
#define IXGBE_PCI_REG_ADDR(hw, reg) \
--
1.9.1
^ permalink raw reply related [flat|nested] 3+ messages in thread[parent not found: <1423703990-29031-1-git-send-email-xuelin.shi-KZfg59tc24xl57MIdRCFDg@public.gmane.org>]
* Re: [PATCH] ixgbe: fix ixgbe PCI access endian issue [not found] ` <1423703990-29031-1-git-send-email-xuelin.shi-KZfg59tc24xl57MIdRCFDg@public.gmane.org> @ 2015-02-20 10:53 ` Thomas Monjalon 2015-03-25 6:33 ` Zhang, Helin 1 sibling, 0 replies; 3+ messages in thread From: Thomas Monjalon @ 2015-02-20 10:53 UTC (permalink / raw) To: xuelin.shi-KZfg59tc24xl57MIdRCFDg; +Cc: dev-VfR2kkLFssw > ixgbe is little endian, but cpu maybe not. > add necessary conversions. > rte_cpu_to_le_32(...) for PCI write > rte_le_to_cpu_32(...) for PCI read. > > Signed-off-by: Xuelin Shi <xuelin.shi-KZfg59tc24xl57MIdRCFDg@public.gmane.org> Acked-by: Thomas Monjalon <thomas.monjalon-pdR9zngts4EAvxtiuMwx3w@public.gmane.org> Applied, thanks ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] ixgbe: fix ixgbe PCI access endian issue [not found] ` <1423703990-29031-1-git-send-email-xuelin.shi-KZfg59tc24xl57MIdRCFDg@public.gmane.org> 2015-02-20 10:53 ` Thomas Monjalon @ 2015-03-25 6:33 ` Zhang, Helin 1 sibling, 0 replies; 3+ messages in thread From: Zhang, Helin @ 2015-03-25 6:33 UTC (permalink / raw) To: xuelin.shi-KZfg59tc24xl57MIdRCFDg@public.gmane.org, thomas.monjalon-pdR9zngts4EAvxtiuMwx3w@public.gmane.org Cc: dev-VfR2kkLFssw@public.gmane.org > -----Original Message----- > From: dev [mailto:dev-bounces-VfR2kkLFssw@public.gmane.org] On Behalf Of > xuelin.shi-KZfg59tc24xl57MIdRCFDg@public.gmane.org > Sent: Thursday, February 12, 2015 9:20 AM > To: thomas.monjalon-pdR9zngts4EAvxtiuMwx3w@public.gmane.org > Cc: dev-VfR2kkLFssw@public.gmane.org > Subject: [dpdk-dev] [PATCH] ixgbe: fix ixgbe PCI access endian issue > > From: Xuelin Shi <xuelin.shi-KZfg59tc24xl57MIdRCFDg@public.gmane.org> > > ixgbe is little endian, but cpu maybe not. > add necessary conversions. > rte_cpu_to_le_32(...) for PCI write > rte_le_to_cpu_32(...) for PCI read. > > Signed-off-by: Xuelin Shi <xuelin.shi-KZfg59tc24xl57MIdRCFDg@public.gmane.org> Acked-by: Helin Zhang <helin.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> > --- > lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h > b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h > index 2d40bfd..f8bfb3f 100644 > --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h > +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h > @@ -119,11 +119,11 @@ typedef int bool; > > static inline uint32_t ixgbe_read_addr(volatile void* addr) { > - return IXGBE_PCI_REG(addr); > + return rte_le_to_cpu_32(IXGBE_PCI_REG(addr)); > } > > #define IXGBE_PCI_REG_WRITE(reg, value) do { \ > - IXGBE_PCI_REG((reg)) = (value); \ > + IXGBE_PCI_REG((reg)) = (rte_cpu_to_le_32(value)); \ > } while(0) > > #define IXGBE_PCI_REG_ADDR(hw, reg) \ > -- > 1.9.1 ^ permalink raw reply [flat|nested] 3+ messages in thread
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2015-02-12 1:19 [PATCH] ixgbe: fix ixgbe PCI access endian issue xuelin.shi-KZfg59tc24xl57MIdRCFDg
[not found] ` <1423703990-29031-1-git-send-email-xuelin.shi-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2015-02-20 10:53 ` Thomas Monjalon
2015-03-25 6:33 ` Zhang, Helin
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