From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Monjalon Subject: Re: [PATCH] fm10K: fix interrupt fault handling Date: Wed, 22 Jul 2015 12:46:40 +0200 Message-ID: <1715547.l9Ey1F3lgG@xps13> References: <1437093202-30265-1-git-send-email-stephen@networkplumber.org> <4341B239C0EFF9468EE453F9E9F4604D0172404A@shsmsx102.ccr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Cc: dev@dpdk.org To: Stephen Hemminger Return-path: Received: from mail-wi0-f173.google.com (mail-wi0-f173.google.com [209.85.212.173]) by dpdk.org (Postfix) with ESMTP id 1F2895921 for ; Wed, 22 Jul 2015 12:47:54 +0200 (CEST) Received: by wibxm9 with SMTP id xm9so95805952wib.1 for ; Wed, 22 Jul 2015 03:47:54 -0700 (PDT) In-Reply-To: <4341B239C0EFF9468EE453F9E9F4604D0172404A@shsmsx102.ccr.corp.intel.com> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > > The fm10k driver was reading the interrupt cause register but then > > using the interrupt mask register defines to look at the bits. > > The result is that if a fault happens, the driver would never clear > > the fault and would get into an infinite cycle of interrupts. > > > > Note: I don't work for Intel or have the hardware manuals (probably > > requires NDA anyway), but this looks logical and matches how the > > known working Linux driver handles these bits. > > > > Signed-off-by: Stephen Hemminger > > Good catch! Thanks! > > Acked-by: Jing Chen Applied, thanks