From mboxrd@z Thu Jan  1 00:00:00 1970
From: Thomas Monjalon <thomas.monjalon@6wind.com>
Subject: Re: [PATCH v3] ixgbe: fix data access on big endian cpu
Date: Fri, 10 Jul 2015 16:51:34 +0200
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References: <1427786750-30308-1-git-send-email-xuelin.shi@freescale.com>
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Xuelin, have you given up with that patch?

2015-04-14 23:11, Ananyev, Konstantin:
> From: xuelin.shi@freescale.com [mailto:xuelin.shi@freescale.com]
> >  			txd->read.olinfo_status =
> > -				rte_cpu_to_le_32(olinfo_status);
> > +					rte_cpu_to_le_32(olinfo_status);
> > +
> 
> Not sure, what had changed here?

> > @@ -2293,7 +2314,8 @@ ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
> >  	rxdp = &(rxq->rx_ring[rxq->rx_tail]);
> > 
> >  	while ((desc < rxq->nb_rx_desc) &&
> > -		(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
> > +		(rte_le_to_cpu_32(rxdp->wb.upper.status_error) &
> > +				  IXGBE_RXDADV_STAT_DD)) {
> 
> Why not ' rxdp->wb.upper.status_error & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)'?
> To keep it consistent with rest of the changes?