From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Monjalon Subject: Re: [PATCH] Fix KNI compiling issue on IBM Power Date: Thu, 04 Dec 2014 14:47:03 +0100 Message-ID: <1795169.cqFrYtuj77@xps13> References: <1417688048-23076-1-git-send-email-chaozhu@linux.vnet.ibm.com> <1950672.AxEg8fkUWW@xps13> <20141204132939.GB16249@hmsreliant.think-freely.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Cc: dev-VfR2kkLFssw@public.gmane.org, Chao Zhu To: Neil Horman Return-path: In-Reply-To: <20141204132939.GB16249-B26myB8xz7F8NnZeBjwnZQMhkBWG/bsMQH7oEaQurus@public.gmane.org> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" 2014-12-04 08:29, Neil Horman: > On Thu, Dec 04, 2014 at 12:59:31PM +0100, Thomas Monjalon wrote: > > > Because of different cache line size, the alignment of struct > > > rte_kni_mbuf in rte_kni_common.h doesn't work on IBM Power. This patch > > > changed from 64 to RTE_CACHE_LINE_SIZE micro to do the alignment. > > > > > > Signed-off-by: Chao Zhu > > > > Acked-by: Thomas Monjalon > > > > Applied > > > Woah! Slow down here, I'm not sure if this makes sense to fix his way. The > exact same ifndef/define/endif construct is used for this macro in rte_memory.h. > Currently their defined to the same vaule, but if that ever changes, this macro > will return different values based on the order in which header files are > included. That doesn't seem appropriate at all. I agree (was my comment) but the patch was applied as a hot fix. A better fix has to be found for DPDK 2.0. Do you agree this fix is enough for DPDK 1.8 release? > > I wonder if we could try to guess the cache line size instead of > > configuring it in many places. > > Maybe we could use something like sysconf(_SC_LEVEL1_DCACHE_LINESIZE)? > > > This is a good idea, but I think its a bit broken for a few reasons: > > 1) _SC_LEVEL1_DCACHE_LINESIZE I don't think is POSIX mandated, so there is every > possibility that the above won't work on BSD > > 2) While getting the cache line size dynamically is a great idea, dpdk has > several locations that size structures based on processor cache line size, which > implicitly requires a static cache line definition. It can be guessed dynamically in the first build step (kind of configure). > It seems the right thing to do, in my mind is to define RTE_CACHE_LINE_SIZE per > arch (perhaps in common/include/arch//rte_.h), then just let > the build break if a given arch doesn't define it (i.e. make definig that value > an arch reqirement). It's the other option. For IBM Power, it's currently overwritten in the Makefile: http://dpdk.org/browse/dpdk/tree/mk/arch/ppc_64/rte.vars.mk Thanks for helping to find a better solution. -- Thomas