From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Monjalon Subject: Re: [memnic PATCH 4/7] pmd: use compiler barrier Date: Wed, 24 Sep 2014 17:18:09 +0200 Message-ID: <1855491.X6obi8qxOV@xps13> References: <7F861DC0615E0C47A872E6F3C5FCDDBD011A9934@BPXM14GP.gisp.nec.co.jp> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Cc: Hayato Momma To: dev-VfR2kkLFssw@public.gmane.org, Hiroshi Shimamoto Return-path: In-Reply-To: <7F861DC0615E0C47A872E6F3C5FCDDBD011A9934-ZmjkEB1lVlLt6d3pZDjeaEtBU8KWyXPq@public.gmane.org> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" 2014-09-11 07:48, Hiroshi Shimamoto: > x86 can keep store ordering with standard operations. Are we sure it's always the case (including old 32-bit CPU)? I would prefer to have a reference here. I know we already discussed this kind of things but having a reference in commit log could help for future discussions. > Using memory barrier is much expensive in main packet processing loop. > Removing this improves xmit/recv packet performance. > > We can see performance improvements with memnic-tester. > Using Xeon E5-2697 v2 @ 2.70GHz, 4 vCPU. > size | before | after > 64 | 4.18Mpps | 4.59Mpps > 128 | 3.85Mpps | 4.87Mpps > 256 | 4.01Mpps | 4.72Mpps > 512 | 3.52Mpps | 4.41Mpps > 1024 | 3.18Mpps | 3.64Mpps > 1280 | 2.86Mpps | 3.15Mpps > 1518 | 2.59Mpps | 2.87Mpps > > Note: we have to take care if we use temporal cache. Please, could you explain this last sentence? Thanks -- Thomas