From mboxrd@z Thu Jan  1 00:00:00 1970
From: Thomas Monjalon <thomas@monjalon.net>
Subject: Re: [PATCH v3 1/2] test/test: introduce new test-case
	for rte_smp_mb()
Date: Tue, 16 Jan 2018 01:16:38 +0100
Message-ID: <1920273.q5HlxWAJJN@xps>
References: <1513611253-8785-2-git-send-email-konstantin.ananyev@intel.com>
 <1516028680-2342-2-git-send-email-konstantin.ananyev@intel.com>
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Cc: dev@dpdk.org, jerin.jacob@caviumnetworks.com
To: Konstantin Ananyev <konstantin.ananyev@intel.com>
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15/01/2018 16:04, Konstantin Ananyev:
> Simple functional test for rte_smp_mb() implementations.
> Also when executed on a single lcore could be used as rough
> estimation how many cycles particular implementation of rte_smp_mb()
> might take.
> 
> Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
> ---
>  test/test/Makefile       |   1 +
>  test/test/test_barrier.c | 286 +++++++++++++++++++++++++++++++++++++++++++++++

I will add
	F: test/test/test_barrier.c
in MAINTAINERS, when applying.

> +static inline void
> +store_load_barrier(uint32_t utype)
> +{
> +	if (utype == USE_MB)
> +		rte_mb();
> +	else if (utype == USE_SMP_MB)
> +		rte_smp_mb();
> +	else
> +		RTE_VERIFY(0);
> +}

It does not compile on ARM64.
I have sent a fix for ARM64 barrier macros:
	https://dpdk.org/patch/33762