From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Monjalon Subject: Re: [PATCH] bus/fslmc: change the eqcr stashing threshold to 1 Date: Fri, 12 Jan 2018 12:47:58 +0100 Message-ID: <1960268.40KerNktNo@xps> References: <1514993944-11940-1-git-send-email-nipun.gupta@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Cc: dev@dpdk.org, Shreyansh Jain , ferruh.yigit@intel.com, hemant.agrawal@nxp.com To: Nipun Gupta Return-path: Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by dpdk.org (Postfix) with ESMTP id BBC53A49F for ; Fri, 12 Jan 2018 12:48:28 +0100 (CET) In-Reply-To: List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 05/01/2018 12:23, Shreyansh Jain: > On Wednesday 03 January 2018 09:09 PM, Nipun Gupta wrote: > > Changing the EQCR stashing threshold boosts the performance > > of l3fwd application on LS2088 by more than 20% as it helps > > in burst packet processing at the Tx side. CPU is immediately > > informed about the empty EQCR entries once consumed by the > > hardware. > > > > Signed-off-by: Nipun Gupta > > Acked-by: Shreyansh Jain Applied, thanks