From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Hemminger Subject: Re: memory barriers in rte_ring Date: Thu, 27 Mar 2014 13:20:13 -0700 Message-ID: <20140327132013.10011e6a@samsung-9> References: <53345655.9030907@6wind.com> <20140327120620.07f1496b@samsung-9> <53348059.6000505@6wind.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: "dev-VfR2kkLFssw@public.gmane.org" To: Olivier MATZ Return-path: In-Reply-To: <53348059.6000505-pdR9zngts4EAvxtiuMwx3w@public.gmane.org> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" On Thu, 27 Mar 2014 20:47:37 +0100 Olivier MATZ wrote: > Hi Stephen, > > On 03/27/2014 08:06 PM, Stephen Hemminger wrote: > > Long answer: for the multple CPU access ring, it is equivalent to smp_wmb and smp_rmb > > in Linux kernel. For x86 where DPDK is used, this can normally be replaced by simpler > > compiler barrier. In kernel there is a special flage X86_OOSTORE which is only enabled > > for a few special cases, for most cases it is not. When cpu doesnt do out of order > > stores, there are no cases where other cpu will see wrong state. > > Thank you for this clarification. > > So, if I understand properly, all usages of rte_*mb() sequencing memory > operations between CPUs could be replaced by a compiler barrier. On the > other hand, if the memory is also accessed by a device, a memory > barrier has to be used. > > Olivier > I think so for the current architecture that DPDK runs on. It might be good to abstract this in some way for eventual users in other environments.