From mboxrd@z Thu Jan 1 00:00:00 1970 From: Neil Horman Subject: Re: [PATCH v2 1/4] app/test: unit test for rx and tx cycles/packet Date: Tue, 21 Oct 2014 09:37:38 -0400 Message-ID: <20141021133738.GC12795@hmsreliant.think-freely.org> References: <1408947174-11323-1-git-send-email-cunming.liang@intel.com> <1412944201-30703-1-git-send-email-cunming.liang@intel.com> <1412944201-30703-2-git-send-email-cunming.liang@intel.com> <20141010175226.GG19499@hmsreliant.think-freely.org> <20141021103315.GB12795@hmsreliant.think-freely.org> <59AF69C657FD0841A61C55336867B5B0344212BF@IRSMSX103.ger.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: "dev-VfR2kkLFssw@public.gmane.org" To: "Richardson, Bruce" Return-path: Content-Disposition: inline In-Reply-To: <59AF69C657FD0841A61C55336867B5B0344212BF-kPTMFJFq+rELt2AQoY/u9bfspsVTdybXVpNB7YpNyf8@public.gmane.org> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" On Tue, Oct 21, 2014 at 10:43:03AM +0000, Richardson, Bruce wrote: > > > > -----Original Message----- > > From: dev [mailto:dev-bounces-VfR2kkLFssw@public.gmane.org] On Behalf Of Neil Horman > > Sent: Tuesday, October 21, 2014 11:33 AM > > To: Liang, Cunming > > Cc: dev-VfR2kkLFssw@public.gmane.org > > Subject: Re: [dpdk-dev] [PATCH v2 1/4] app/test: unit test for rx and tx > > cycles/packet > > > > > > > > > > > + if (count == 0) > > > > > + return -1; > > > > > + > > > > > + printf("%lu packet, %lu drop, %lu idle\n", count, drop, idle); > > > > > + printf("Result: %ld cycles per packet\n", (cur_tsc - prev_tsc) / count); > > > > > + > > > > Bad math here. Theres no guarantee that the tsc hasn't wrapped (potentially > > > > more than once) depending on your test length. you need to check the tsc > > before > > > > and after each burst and record an average of deltas instead, accounting in > > each > > > > instance for the possibility of wrap. > > > [Liang, Cunming] I'm not sure catch your point correctly. > > > I think both cur_tsc and prev_tsc are 64 bits width. > > > For 3GHz, I think it won't wrapped so quick. > > > As it's uint64_t, so even get wrapped, the delta should still be correct. > > But theres no guarantee that the tsc starts at zero when you begin your test. > > The system may have been up for a long time and near wrapping already. > > Regardless, you need to account for the possibility that cur_tsc is smaller > > than prev_tsc, or this breaks. > > > > The tsc. is 64-bit and so only wraps around every couple of hundred years or so on a 2GHz machine, so I don't think it's necessary to handle that case. > But that presumes that no one has written the TSC via IA32_TIME_STAMP_COUNTER. Assuming that something will never wrap just seems like bad practice here. We should have a general purpose macro to handle wrapping counters like this, if not for this case specficially, then in general. Neil > /Bruce >