From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bruce Richardson Subject: Re: Relationship between H/W ring and S/W ring Date: Fri, 31 Oct 2014 10:08:17 +0000 Message-ID: <20141031100817.GA4948@bricha3-MOBL3> References: <5451E980.2060707@gmail.com> <20141030095522.GA4460@bricha3-MOBL3> <5452DD2C.8030402@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Cc: dev-VfR2kkLFssw@public.gmane.org To: Gyumin Return-path: Content-Disposition: inline In-Reply-To: <5452DD2C.8030402-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" On Fri, Oct 31, 2014 at 09:51:56AM +0900, Gyumin wrote: > Thanks Bruce. >=20 > I also agree with that the size of the S/W ring depends on the configur= ation > parameters because the size of the S/W ring is /sizeof(struct igb_rx_en= try) > * len/ in the ixgbe_dev_rx_queue_setup function. H/W ring is also alloc= ated > in the same function by using the ring_dma_zone_reserve function, and i= ts > size is RX_RING_SZ. I don't think the RX_RING_SZ is configurable but it= is > fixed value. Is there any other code configuring the size of H/W ring? >=20 Indeed you are right, my mistake. The comment indicates that we always re= serve the memory to be the maximum size so that we can resize the rings easier = later on. In terms of runtime usage, though, if you look a the RX functions, you ca= n see that the two rings are always kept in sync. For example, looking at=20 ixgbe_rxq_rearm in ixgbe_rxtx_vec.c, you will see that rxdp and rxep valu= es both start at offset "rxq->rxrearm_start" at the top of the function, and= that in the main rearm loop, both are incremented twice each iteration (rxep += =3D 2 in the for statment itself, and two rxdp++'s are used in the last two lines = of the loop body). Regards, /Bruce > 2014-10-30 =EC=98=A4=ED=9B=84 6:55=EC=97=90 Bruce Richardson =EC=9D=B4(= =EA=B0=80) =EC=93=B4 =EA=B8=80: > >On Thu, Oct 30, 2014 at 04:32:16PM +0900, Gyumin wrote: > >>Hi > >> > >>I`m reading the ixgbe code especially about H/W ring and S/W ring. Is= the > >>relationship between H/W ring and S/W ring one-to-one mapping? > >>As far as I know, H/W ring size is determined in the code(hard coded)= while > >>S/W ring size is determined in port configuration time. > >>In the ixgbe_rx_alloc_bufs function, H/W ring header address and pack= et > >>address indicate the DMA address of S/W ring's mbuf. I understand it = means > >>that the relationship between the H/W ring and S/W ring is one-to-one > >>mapping. For example, if the size of H/W ring is greater than the siz= e of > >>S/W ring then some portion of H/W ring is unused. Is it correct? > >> > >>Thanks > >Hi, > > > >Yes, there is a 1:1 mapping between the hardware and software ring ent= ries, and both are sized depending on the configuration parameters passed= to the ring setup APIs. As you state, the HW ring contains the DMA addre= sses of the packet buffers, while the sw_ring contains the pointers to th= e original mbufs. The two rings are always kept in sync in the code. > > > >/Bruce > > >=20