From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Hemminger Subject: Re: [PATCH] ixgbe:Add write memory barrier for recv pkts. Date: Wed, 15 Apr 2015 09:06:42 -0700 Message-ID: <20150415090642.0137f4c9@urahara> References: <2601191342CEEE43887BDE71AB97725821415A3A@irsmsx105.ger.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: "dev-VfR2kkLFssw@public.gmane.org" To: "Dong.Wang" Return-path: In-Reply-To: List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" On Wed, 15 Apr 2015 21:46:27 +0800 Dong.Wang wrote: > Yes, current implementation works well with IA, and the transmit packets > function's rte_wmb() is also unneccessary. > > But there are two reasons for adding rte_wmb() in recv pkts function: > 1) The memory barrier in recv pkts function and xmit pkts function are > inconsistent, rte_wmb() should be added to recv pkts function or be > removed from xmit pkts function. > 2) DPDK will support PowerPC processor (Other developers are working on > it), I check the memory ordering of PowerPC, there was no mention of > store-store instruction's principle in MPC8544 Reference Manual, only > said it is weak memory ordering. > > So, I think it is neccessary to add rte_wmb() to recv pkts function. > > Dong If PowerPC requires additional memory barriers then it should introduce a new generic set of memory barrier macros that are no-ops on other architectures. Please don't penalize x86 for places where other CPU's have weaker consistency.