From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bruce Richardson Subject: Re: Minimum Supported x86 microarchitecture Date: Wed, 15 Apr 2015 17:05:27 +0100 Message-ID: <20150415160527.GA9836@bricha3-MOBL3> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: "dev-VfR2kkLFssw@public.gmane.org" To: "Kavanagh, Mark B" Return-path: Content-Disposition: inline In-Reply-To: List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" On Wed, Apr 15, 2015 at 03:09:39PM +0000, Kavanagh, Mark B wrote: > Hi, > > The recent reimplementation of rte_memcpy in DPDK v2.0.0 seems to have a placed an implicit floor on the microarchitecture/Instruction set supported by DPDK. > > For example, I can't compile head of OVS against DPDK 2.0 with gcc without passing the 'msse3' flag; this points to an implicit minimum supported CPU of 'core2'. More discussion on same is available here: http://openvswitch.org/pipermail/dev/2015-April/053523.html > > Can anyone confirm or deny this, and is/should it be documented? > > Thanks in advance, > Mark SSE3 is the minimum necessary. However, I believe all x86_64 cpus have at least SSE3 support, so this should only be a problem with 32-bit builds. Is this the case for you? /Bruce