From mboxrd@z Thu Jan  1 00:00:00 1970
From: Cyril Chemparathy <cchemparathy@ezchip.com>
Subject: Re: [PATCH v2 12/12] mk: introduce Tilera Tile
 architecture
Date: Fri, 22 May 2015 12:42:39 -0400
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On Fri, 22 May 2015 18:03:04 +0200
Thomas Monjalon <thomas.monjalon@6wind.com> wrote:

> Hi,
> 
> 2015-01-06 14:53, Zhigang Lu:
> > Add defconfig and rte.vars.mk files for Tile architecture.
> > 
> > Signed-off-by: Zhigang Lu <zlu@ezchip.com>
> > Signed-off-by: Cyril Chemparathy <cchemparathy@ezchip.com>
> 
> This series is pending without having any comments.
> So it should be accepted and merged.
> 

I'm working on a refresh to the latest master.  In the process, I've
simplified most of the patches down to bare essentials.

Since the TILE-Gx platform is a strict alignment machine, we need
alignment related fixes that have been submitted previously (see
http://www.dpdk.org/ml/archives/dev/2015-April/017090.html).  These are
based on relatively recent contents of master, and therefore should be
ready to merge once we go through the review cycle.  Would you mind
taking a look at these?

> Do you accept to be the maintainer of Tile architecture?
> If you agree, please respin this series with a cover letter (it was
> missing in this v2) and update the MAINTAINERS file.
> 

Sure.  We'll internally figure out the appropriate maintainer and
include this in the next round of patches.


Thanks
-- Cyril.