From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jerin Jacob Subject: Re: [PATCH v3 1/4] eal: Introduce new cache macro definitions Date: Wed, 6 Jan 2016 20:40:46 +0530 Message-ID: <20160106151032.GA20958@localhost.localdomain> References: <1449765378-29563-1-git-send-email-jerin.jacob@caviumnetworks.com> <1450067576-18803-1-git-send-email-jerin.jacob@caviumnetworks.com> <1450067576-18803-2-git-send-email-jerin.jacob@caviumnetworks.com> <568A7089.3070506@6wind.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Cc: dev@dpdk.org To: Olivier MATZ Return-path: Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1bon0053.outbound.protection.outlook.com [157.56.111.53]) by dpdk.org (Postfix) with ESMTP id 0255E95B7 for ; Wed, 6 Jan 2016 16:11:11 +0100 (CET) Content-Disposition: inline In-Reply-To: <568A7089.3070506@6wind.com> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Mon, Jan 04, 2016 at 02:15:53PM +0100, Olivier MATZ wrote: > Hi Jerin, Hi Olivier, > > Please see some comments below. > > On 12/14/2015 05:32 AM, Jerin Jacob wrote: > > - RTE_CACHE_MIN_LINE_SIZE(Supported minimum cache line size) > > - __rte_cache_min_aligned(Force minimum cache line alignment) > > - RTE_CACHE_LINE_SIZE_LOG2(Express cache line size in terms of log2) > > > > Signed-off-by: Jerin Jacob > > Suggested-by: Konstantin Ananyev > > --- > > lib/librte_eal/common/include/rte_memory.h | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/lib/librte_eal/common/include/rte_memory.h b/lib/librte_eal/common/include/rte_memory.h > > index 9c9e40f..b67a76f 100644 > > --- a/lib/librte_eal/common/include/rte_memory.h > > +++ b/lib/librte_eal/common/include/rte_memory.h > > @@ -77,11 +77,27 @@ enum rte_page_sizes { > > (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE)) > > /**< Return the first cache-aligned value greater or equal to size. */ > > > > +/**< Cache line size in terms of log2 */ > > +#if RTE_CACHE_LINE_SIZE == 64 > > +#define RTE_CACHE_LINE_SIZE_LOG2 6 > > +#elif RTE_CACHE_LINE_SIZE == 128 > > +#define RTE_CACHE_LINE_SIZE_LOG2 7 > > +#else > > +#error "Unsupported cache line size" > > +#endif > > + > > +#define RTE_CACHE_MIN_LINE_SIZE 64 /**< Minimum Cache line size. */ > > + > > I think RTE_CACHE_LINE_MIN_SIZE or RTE_MIN_CACHE_LINE_SIZE would > be clearer than RTE_CACHE_MIN_LINE_SIZE. OK. I will resend the next version with RTE_CACHE_LINE_MIN_SIZE > > > /** > > * Force alignment to cache line. > > */ > > #define __rte_cache_aligned __rte_aligned(RTE_CACHE_LINE_SIZE) > > > > +/** > > + * Force minimum cache line alignment. > > + */ > > +#define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_MIN_LINE_SIZE) > > I'm not really convinced that __rte_cache_min_aligned is straightforward > for someone reading the code that it means "aligned to the minimum cache > line size supported by the dpdk". > > In the two cases you are using this macro (mbuf structure and queue > info), I'm wondering if using __attribute__((aligned(64))) wouldn't be > clearer? > - for mbuf, it could be a local define, like MBUF_ALIGN_SIZE > - for queue info, using 64 makes sense as it's used to reserve space > for future use > > What do you think? IMO, it makes sense to keep "__rte_cache_min_aligned" as it will useful for forcing the minimum alignment requirements in DPDK in future structures. Thoughts? > > > Regards, > Olivier