From mboxrd@z Thu Jan  1 00:00:00 1970
From: Bruce Richardson <bruce.richardson@intel.com>
Subject: Re: [PATCH 0/6] DPDK PMD for new QLogic FastLinQ QL4xxxx
 25G/40G CNAs
Date: Tue, 8 Mar 2016 14:01:49 +0000
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To: Harish Patil <harish.patil@qlogic.com>
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On Sat, Feb 20, 2016 at 07:40:25AM -0800, Harish Patil wrote:
> This patch set introduces DPDK poll mode driver for new QLogic FastLinQ QL4xxxx
> 25G/40G capable family of CNAs as well as their SR-IOV Virtual Functions (VF).
> 
> The overall PMD driver design includes a common module called ecore that deals
> with the low level HW and a upper layer portion that provides the glue logic.
> 
> Specifically, the ecore module contains all of the common logic,
> e.g. initialization, cleanup, infrastructure for interrupt handling, link
> management, slowpath etc. as well as protocol agnostic features and supplying
> an abstraction layer for other modules.
> 
> The higher layer implements DPDK exported APIs/driver entry points by
> interfacing with the common module for configuration/status and also the
> fastpath routines.
> 
> Included in the patch set is the supporting documentation and maintainers.
> 
> Please apply.
> 
> Thanks,
> 
> Harish Patil (6):
>   qede: add maintainers
>   qede: add documentation
>   qede: add QLogic PCI ids
>   qede: add driver common module
>   qede: add driver
>   qede: enable PMD build
Hi Harish,

there are quite a few comments to be addressed on this patchset. Are there plans
for a V2 in time for the code freeze deadline later this week?

	/Bruce