From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bruce Richardson Subject: Re: [PATCH] i40e: improve performance of vector PMD Date: Thu, 14 Apr 2016 14:50:24 +0100 Message-ID: <20160414135024.GA25840@bricha3-MOBL3> References: <1460628921-25635-1-git-send-email-bruce.richardson@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Cc: Helin Zhang , Jingjing Wu To: dev@dpdk.org Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 65ACC2965 for ; Thu, 14 Apr 2016 15:50:28 +0200 (CEST) Content-Disposition: inline In-Reply-To: <1460628921-25635-1-git-send-email-bruce.richardson@intel.com> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Thu, Apr 14, 2016 at 11:15:21AM +0100, Bruce Richardson wrote: > An analysis of the i40e code using Intel=C2=AE VTune=E2=84=A2 Amplifier= 2016 showed > that the code was unexpectedly causing stalls due to "Loads blocked by > Store Forwards". This can occur when a load from memory has to wait > due to the prior store being to the same address, but being of a smalle= r > size i.e. the stored value cannot be directly returned to the loader. > [See ref: https://software.intel.com/en-us/node/544454] >=20 > These stalls are due to the way in which the data_len values are handle= d > in the driver. The lengths are extracted using vector operations, but t= hose > 16-bit lengths are then assigned using scalar operations i.e. 16-bit > stores. >=20 > These regular 16-bit stores actually have two effects in the code: > * they cause the "Loads blocked by Store Forwards" issues reported > * they also cause the previous loads in the RX function to actually be = a > load followed by a store to an address on the stack, because the 16-bit > assignment can't be done to an xmm register. >=20 > By converting the 16-bit stores operations into a sequence of SSE blend > operations, we can ensure that the descriptor loads only occur once, an= d > avoid both the additional store and loads from the stack, as well as th= e > stalls due to the second loads being blocked. >=20 > Signed-off-by: Bruce Richardson >=20 Self-NAK on this version. The blend instruction used is SSE4.1 so breaks = the "default" build. Two obvious options to fix this: 1. Keep the old code with SSE4.1 #ifdefs separating old and new 2. Update the vpmd requirement to SSE4.1, and factor that in during runti= me select of the RX code path. Personally, I prefer the second option. Any objections? /Bruce