From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bruce Richardson Subject: Re: [PATCH v2] ixgbe: fix bad shift operation in ixgbe_set_pool_rx/tx Date: Mon, 25 Apr 2016 11:38:08 +0100 Message-ID: <20160425103807.GB18116@bricha3-MOBL3> References: <1460727549-4380-1-git-send-email-tomaszx.kulasek@intel.com> <1461339357-8048-1-git-send-email-tomaszx.kulasek@intel.com> <20160425103543.GA18116@bricha3-MOBL3> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: wenzhuo.lu@intel.com, helin.zhang@intel.com, konstantin.ananyev@intel.com, dev@dpdk.org To: Tomasz Kulasek Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 0892D2A1A for ; Mon, 25 Apr 2016 12:38:13 +0200 (CEST) Content-Disposition: inline In-Reply-To: <20160425103543.GA18116@bricha3-MOBL3> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Mon, Apr 25, 2016 at 11:35:44AM +0100, Bruce Richardson wrote: > On Fri, Apr 22, 2016 at 05:35:57PM +0200, Tomasz Kulasek wrote: > > Fix issue reported by Coverity. > > > > Coverity ID 13193: Bad bit shift operation (BAD_SHIFT) > > large_shift: In expression 1 << pool, left shifting by more than 31 bits > > has undefined behavior. The shift amount, pool, is at least 32. > > > > This patch is a rework of register addr selection logic and mask > > computation to made it more readable and avoid bit overflow when 32 bit > > value is shifted over its size for pool > 31. > > > > Fixes: fe3a45fd4104 ("ixgbe: add VMDq support") > > > > Signed-off-by: Tomasz Kulasek > > Acked-by: Bruce Richardson > Applied to dpdk-next-net/rel_16_07 /Bruce