From mboxrd@z Thu Jan  1 00:00:00 1970
From: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Subject: Re: [PATCH 23/28] net/ixgbe: use eal I/O device memory
 read/write API
Date: Thu, 15 Dec 2016 20:40:19 -0800
Message-ID: <20161216044017.GA29607@santosh-Latitude-E5530-non-vPro>
References: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
 <1481680558-4003-24-git-send-email-jerin.jacob@caviumnetworks.com>
 <CAP4Qi38Bp6oL7uQcOoUqFHk53ARS3Yd+RKw4w1XeHUC+aveEMw@mail.gmail.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Cc: Jerin Jacob <jerin.jacob@caviumnetworks.com>, <dev@dpdk.org>, "Ananyev,
 Konstantin" <konstantin.ananyev@intel.com>, Thomas Monjalon
 <thomas.monjalon@6wind.com>, Bruce Richardson <bruce.richardson@intel.com>,
 Jan Viktorin <viktorin@rehivetech.com>, Helin Zhang <helin.zhang@intel.com>
To: Jianbo Liu <jianbo.liu@linaro.org>
Return-path: <dev-bounces@dpdk.org>
Received: from NAM01-SN1-obe.outbound.protection.outlook.com
 (mail-sn1nam01on0055.outbound.protection.outlook.com [104.47.32.55])
 by dpdk.org (Postfix) with ESMTP id 1D1B93990
 for <dev@dpdk.org>; Fri, 16 Dec 2016 05:40:30 +0100 (CET)
Content-Disposition: inline
In-Reply-To: <CAP4Qi38Bp6oL7uQcOoUqFHk53ARS3Yd+RKw4w1XeHUC+aveEMw@mail.gmail.com>
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <http://dpdk.org/ml/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://dpdk.org/ml/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <http://dpdk.org/ml/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>

On Thu, Dec 15, 2016 at 04:37:12PM +0800, Jianbo Liu wrote:
> On 14 December 2016 at 09:55, Jerin Jacob
> <jerin.jacob@caviumnetworks.com> wrote:
> > From: Santosh Shukla <santosh.shukla@caviumnetworks.com>
> >
> > Replace the raw I/O device memory read/write access with eal
> > abstraction for I/O device memory read/write access to fix
> > portability issues across different architectures.
> >
> > Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
> > Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> > CC: Helin Zhang <helin.zhang@intel.com>
> > CC: Konstantin Ananyev <konstantin.ananyev@intel.com>
> > ---
> >  drivers/net/ixgbe/base/ixgbe_osdep.h | 13 +++++++++----
> >  1 file changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/net/ixgbe/base/ixgbe_osdep.h b/drivers/net/ixgbe/base/ixgbe_osdep.h
> > index 77f0af5..9d16c21 100644
> > --- a/drivers/net/ixgbe/base/ixgbe_osdep.h
> > +++ b/drivers/net/ixgbe/base/ixgbe_osdep.h
> > @@ -44,6 +44,7 @@
> >  #include <rte_cycles.h>
> >  #include <rte_log.h>
> >  #include <rte_byteorder.h>
> > +#include <rte_io.h>
> >
> >  #include "../ixgbe_logs.h"
> >  #include "../ixgbe_bypass_defines.h"
> > @@ -121,16 +122,20 @@ typedef int               bool;
> >
> >  #define prefetch(x) rte_prefetch0(x)
> >
> > -#define IXGBE_PCI_REG(reg) (*((volatile uint32_t *)(reg)))
> > +#define IXGBE_PCI_REG(reg) ({                  \
> > +       uint32_t __val;                         \
> > +       __val = rte_readl(reg);                 \
> > +       __val;                                  \
> > +})
> >
> >  static inline uint32_t ixgbe_read_addr(volatile void* addr)
> >  {
> >         return rte_le_to_cpu_32(IXGBE_PCI_REG(addr));
> >  }
> >
> > -#define IXGBE_PCI_REG_WRITE(reg, value) do { \
> > -       IXGBE_PCI_REG((reg)) = (rte_cpu_to_le_32(value)); \
> > -} while(0)
> > +#define IXGBE_PCI_REG_WRITE(reg, value) ({             \
> > +       rte_writel(rte_cpu_to_le_32(value), reg);       \
> > +})
> >
> 
> memory barrier operation is put inside IXGBE_PCI_REG_READ/WRITE in
> your change, but I found rte_*mb is called before these macros in some
> places.
> Can you remove all these redundant calls? And please do the same
> checking for other drivers.
>

Ok.

Thinking of adding _relaxed_rd/wr style macro agnostic to arch for ixgbe case 
in particular. Such that for those code incident:
x86 case> first default barrier + relaxed call.
arm case> first default barrier + relaxed call.

Does that make sense to you? If so then will take care in v2.

Santosh.


> >  #define IXGBE_PCI_REG_ADDR(hw, reg) \
> >         ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
> > --
> > 2.5.5
> >