From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bruce Richardson Subject: Re: [PATCH 2/2] net/ixgbe: calculate correct number of received packets for ARM NEON-version vPMD Date: Wed, 21 Dec 2016 11:03:32 +0000 Message-ID: <20161221110331.GA9108@bricha3-MOBL3.ger.corp.intel.com> References: <1482127758-4904-1-git-send-email-jianbo.liu@linaro.org> <1482127758-4904-2-git-send-email-jianbo.liu@linaro.org> <20161221100848.GA4506@localhost.localdomain> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Jianbo Liu , dev@dpdk.org, helin.zhang@intel.com, konstantin.ananyev@intel.com To: Jerin Jacob Return-path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id E341410BFF for ; Wed, 21 Dec 2016 12:03:38 +0100 (CET) Content-Disposition: inline In-Reply-To: <20161221100848.GA4506@localhost.localdomain> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Wed, Dec 21, 2016 at 03:38:51PM +0530, Jerin Jacob wrote: > On Mon, Dec 19, 2016 at 11:39:18AM +0530, Jianbo Liu wrote: > > Hi Jianbo, > > > vPMD will check 4 descriptors in one time, but the statuses are not consistent > > because the memory allocated for RX descriptors is cacheable huagepage. > Is it different in X86 case ?i.e Is x86 creating non cacheable hugepages? This is not a problem on IA, because the instruction ordering rules on IA guarantee that the reads will be done in the correct program order, and we never get stale cache data. /Bruce